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Page Title:
Figure 3. Synchronous switching test circuit and waveforms (device types 02 and 52)-cont. |
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|  MIL-M-38510/653B
NOTES:
1. CLEAR and PRESET pulses are active low and dominate regardless of the state of the clock and
data inputs.
2. CLEAR or PRESET input pulse characteristics are as follows:
tr = tf ≤ 6 ns; tp (CLEAR) = tp (PRESET) ≤ 30 ns; tREM ≤ 38 ns.
3. CL = 50 pF 10 % (including test jig and probe capacitance).
4. While testing the CLEAR input at a logic "0" level, PRESET will have a logic "1" level applied.
While testing the PRESET input at a logic level "0", CLEAR will have a logic "1" applied.
5. Voltage measurements are to be made with respect to the network ground terminal. The input signal(s) for
HCT device type 52 will be 0 V to 3 V; however, the 50 % measurements point is 1.3 V for inputs and outputs.
FIGURE 3. CLEAR switching test circuit and waveforms (device types 02 and 52) - Continued.
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