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| TABLE III. Group A inspection Continued.
1/
Pins not designated may be high level logic, low level logic, or open. Exceptions are as follows:
a. VIC(pos) tests, the GND terminal shall be open. For test equipment that does not allow GND pin to be open during test, a minimum limit of 0.4 V applies.
b. VIC(neg) tests, the VCC terminal shall be open.
c. IIC tests, the output terminals shall be open.
2/
Apply one clock pulse prior to test as follows: 6.0 V
or
6.0 V
as appropriate.
0.0 V
0.0 V
3/
Apply one clock pulse prior to test as follows: 4.0 V
or
4.0 V
as appropriate.
0.0 V
0.0 V
4/
See 4.4.1c.
5/
A = 3.7 V, B = 0.4 V for all device types (except 52 where A = 2.4 V); H > 2.5 V, L < 2.5 V.
6/
Only a summary of attributes data is required.
7/
Apply input test parameters such that tsu, thold, trem, and tw values are not greater than the recommended operating minimums (see 1.4).
Preset outputs to required state if necessary prior to test.
8/
See 4.4.1d.
9/
The fMAX, minimum limit specified, is the frequency of the clock input. The data input is fMAX/2
10/ Apply one clock pulse prior to test as follows: 4.5 V
or
4.5 V
as appropriate.
0.0 V
0.0 V
11/ Three-state output conditions are required.
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