Microcircuit, Digital, CMOS (Initial Logic)

Click here to make tpub.com your Home Page

Page Title: Microcircuit, Digital, CMOS (Initial Logic)

Click here for thousands of PDF manuals

Web
www.tpub.com

Information Categories

....

Administration
Advancement
Aerographer
Automotive
Aviation
Construction
Diving
Draftsman
Engineering
Electronics
Food and Cooking
Logistics
Math
Medical
Music
Nuclear Fundamentals
Photography
Religion

Microcircuit, Digital, CMOS (Initial Logic)

Microcircuit, Digital, CMOS (Initial Logic)
Device classification
Operating ratings
Table 2. Electrical Parameters
Device marking.
Metallization.
Quality Assurance Provisions
Requalification
Table 3. First article inspection
Microcircuit, Digital, CMOS (Initial logic)
Microcircuit, Digital, CMOS (Initial logic)-cont.
Inspection lot formation
Classification of Defects & Tests
Microcircuits, Digital, CMOS (Initial Logic)
Microcircuits, Digital, CMOS (Initial Logic)-cont.
Microcircuits, Digital, CMOS (Initial Logic)-cont.
Testing sequence
Leakage current oscillator.
Switching point.
Burn-in screen.
Ordering data.
Changes from previous issue.
Figure 1. Test circuit for Leakage Current (Oscillator) and Oscillator Function Tests
Table 4. Leakage Current Low Test Requirements
Figure 2. Test Set-up for Leakage Current Low Requirement
Figure 3. Test Set up for LVD Switching Point Requirement
Figure 4. Test Set up for Functional Tests
Figure 5. Functional Logic Timing Diagram (Pre-Scaler)
Figure 6. Functional Logic Timing Diagram (Output Signals PA, T, Q, C)
Figure 7. Functional Logic Timing Diagram (Target Signal)
Figure 8. Functional Logic Timing Diagram (LVD)
Figure 9. Functional Logic Timing Diagram - Target Signal, Pre-Enable
Figure 10. Functional Logic Timing Diagram - LVD, Pre-Enable
Figure 11. Functional Logic Timing Diagram (Antidisturbance, AD, Post Enable High to Low)
Figure 12. Functional Logic Timing Diagram (AD, Pre-Enable, High to Low)
Figure 13. Functional Logic Timing Diagram (AD, Post Enable, Low to High)
Figure 14. Functional Logic Timing Diagram (AD, Pre-Enable, Low to High)
Figure 15. Burn-In and Steady State Life-Test Circuit
Figure 16. Static discharge test circuit
Table 6. Signal Summary

Microcircuit, Digital, CMOS (Initial Logic)

Privacy Statement - Press Release - Copyright Information. - Contact Us

Integrated Publishing, Inc. - A (SDVOSB) Service Disabled Veteran Owned Small Business