 |
|||
|
|
|||
| ||||||||||
|
|  MIL-N-81497A(AS)
3.5.5.5
(Continued)
(5) Memory capacity shall be sufficient to perform the
calculations, control functions and interface opera-
tion required for the performance of the INS as
specified herein.
Number System - The Computer, Navigation Number
3.5.5.6
system shall be: fixed point, binary whole number.
3.5.5.7
Modes of Operation -
3.5.5.7.1 Read/Restore Mode - Binary digit information read out
of core locations during the read cycle of this mode shall be re-
written in the same core during the restore cycle.
3.5.5.7.2 Clear/Write Mode - Binary digit information read out
of the core locations during the clear cycle of this mode shall be
replaced by new data bits in these core locations during the write
cycle.
Only the Scratch Pad memory shall be capable of clear/write
operation, to enable updated digital information to be entered into
storage.
Arithmetic and Control - The Computer, Navigation
3.5.5.8
shall contain arithmetic and control logic of a general purpose design,
capable of performing the following functions:
(1)
Capable of performing 22 basic orders including double
precision operations.
Controlling and addressing the core memory
(2)
Performing arithmetic operations, using binary whole
(3)
number, two's complement operands of up to 19 bits
plus sign bit.
The capability for both program interrupt and idle
(4)
time memory usage. Program interrupt may be either
real time program interrupt or external equipment
interrupt.
3.5.5.9
Arithmetic and Control Timing - The Computer, Nav-
igation master oscillator shall provide a 4 MC clock rate. Binary
digit counting shall be performed by a bit counter. which shall have
a 10 bit capacity and a 1 MC (1 bit/ SEC) clockrate.
3.5.5.9.1 Addition Time - 20 SEC maximum
44
|
|
Privacy Statement - Press Release - Copyright Information. - Contact Us |
Click
here for thousands of PDF manuals