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| MIL-N-81497A(AS)
100" Twisted Pair
equivalent characteristic
impedance of ≈ 150 ohms.
With the above configuration the following performance will
be maintained.
Voltage levels at output terminals will be:
(1)
0 0.5V
logic 1:
logic 0: +4 1V
Threshold level of receiver, distinguishing the logic
(2)
1 from the logic 0 is +1.5 0.5V at the receiver terminals.
The circuit will be capable of 5V common mode noise
(3)
rejection.
Rise and fall times as measured from the 10 to 90 percent
(4)
of full amplitude at the output terminals will not be
greater than 1 SEC.
The maximum steady state current drawn from a line by the
(5)
receiver will not exceed 3 MA.
Figure 4
Input/Output Circuit Characteristics
(INS//Doppler and INS//Data Processing System)
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