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| MIL-N-81604C(AS)
Para 3.4.4.3.1b
(cont)
Request Register with an address which tells
the CAU what to do. In addition, at this
time, the Request Ready discrete shall go to
the true (high) state.
The CAU can then, under its own controll call
for the contents of the Request Register.
This is accomplished by holding Sync = 0 and
transmitting a 6 or 7 bit-time envelope on
Data 1. Under control of this envelope, the
Request Register is shifted out on Data 2.
Again a "l" shall be added to the leading edge
of the data transmitted on Data 2. Upon
completion of this transmission (end of the
envelope consisting of Data 1 and Sync not)
the Request Ready discrete shall be removed.
Signal Description - The ANCU/CAU timing dia-
c.
*
qrams are presented in figures 10, 11, and 12.
*
Figure 13 depicts the ANCU/CAU serial data
format and signal relationships.
(1) Clock 1 (CAU to ANCU) - A clock between
1 and 6 MHz may be supplied to the ANCU.
The ANCU line receiver shall be a Type
D circuit.
(2) Clock 2 (ANCU to CAU) - This clock shall
be a retransmitted version of the clock
from the CAU and shall be used for gating
the serial data into the CAU. The ANCU
line driver shall be a Type D circuit.
(3) Sync (CAU to ANCU) - The true state of
this sync signal shall be the envelope
from the CAU which shall be used for
gating information into and out of the
ANCU in the data mode. The ANCU line
receiver shall be a Type D circuit.
(4) Data 1 - Data 1 shall be the serial data
line the CAU to the ANCU. See
figure 13 for a description of the serial *
data word format. The particular infor-
mation which is transmitted is a function
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