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|  MIL-N-81604C(AS)
Appendix I
Para 30.5.8.3
(cont)
b.
CIG Message Gate - This message gate from the
CAU shall bracket all bits in the CIG message.
*
Refer to 30.5.8.3. The CAU line driver shall
be a Type 2 circuit.
CIG Message - This message from the CAU shall
c.
contain true heading and magnetic heading.
Refer to 30.5.8.3. The CAU line driver shall be *
a Type 2-circuit.
CIG Clock - The CAU shall provide a 1.2-MHz
d.
clock to the CIG for clocking the CIG message.
This clock shall always be available when air-
craft power is on, regardless of a CAU power
supply failure or a CIU off condition. The
accuracy shall be 0.1 percent and the pulse
width shall be 100 25 nanoseconds. The CAU
line driver shall be a Type 2 circuit.
30.5.8.4 CAU/DOPLR Serial Interface - The CAU shall initiate
a message request to the doppler as a result of having received
*
the proper six-bit request code from the ANCU (EOP mode) via
Data 2 (table XXIII). The DOPLR shall then respond with a 32-bit *
message gate and message. The message request from the CAU
shall return to its false state within 10 S of the leading edge
of the message gate. The CAU shall provide a 1.2-MHz clock for
clocking data into the CAU. The leading edge of a data bit
from the DOPLR with respect to the leading edge of the CAU clock
shall be within 200 ns. The data from the DOPLR shall be trans-
mitted, MSB first, in the format shown in figure 38. The 32-
bit message shall go through a 3-bit delay in being shifted into
the first 27-bit positions of the CAU serial data register. The
DOPLR data shall then be shifted out, MSB first, of the serial
data register to the ANCU via Data 1 for interleave into memory.
*
Refer to 30.5.10.1.
DOPLR Message Request - This message request
a.
from the CAU shall be answered by the DOPLR
*
with a message gate and a message. Refer to
30.5.8.4.
The CAU line driver shall be a Type
1 circuit.
b.
DOPLR Message Gate - This message gate from the
DOPLR shall bracket all bits in the DOPLR mes-
sage. Refer to 30.5.8.4. The CAU line receiver
*
shall be a Type 2 circuit.
174
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