 |
|||
|
|
|||
| ||||||||||
|
|  MIL-N-85005A(AS)
(4) Execution Times:
DOUBLE PRECISION
SINGLE PRECISION
1.0 sec
1.0 sec
Add/Subtract
5.5 sec
3.5 sec
Multiply
18.75 sec
10.75 sec
Divide
(5) Execution times include:
(a)
Instruction look-ahead fetch
(b)
Obtain two operands from file registers
(c)
Complete operation
(d)
Return result to file register
File Registers - The NC shall contain 16 file registers
3.5.7.4.2
Access time shall be less than 15 nanoseconds.
each 16 bits long.
Memory - The NC shall be capable of accepting up to 32K
3.5.7.4.3
words of programmable memory. The words are 16 bits long. The memory shall
operate at 1.0 microseconds maximum cycle time with 0.5 microseconds maximum
access time.
Memory Protection - A memory protect capability shall
3.5.7.4.3.1
be provided in the logic of the memory address circuits and shall operate
as follows:
The region of lower memory shall be protected by establish-
ing a hard wired address into the memory address logic. This address shall
form a fixed boundary below which no write operation is allowed. If a write
is attempted into an address below the protect boundary, the memory cycle
shall be aborted and an interrupt is generated.
Addressing Modes - As a minimum the NC shall be capable
3.5.7.4.3.2
of addressing the following modes:
A.
Absolute
B.
Indirect
C.
Indexed
D.
Immediate Operand
E.
Relative addressing
Memory Loading - Control lines shall be incorporated at
3.5.7.4.3.3
the external connectors to provide loading, modifying or extracting of
contents of memory through the use of external equipment.
- 96 -
|
|
Privacy Statement - Press Release - Copyright Information. - Contact Us |
Click
here for thousands of PDF manuals