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Page Title:
Figure 2. Truth tables and timing diagrams Device type 03 |
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|  MIL-M-38510/306E
Device type 03
MODE
CLOCKS
PARALLEL
QB
QC
QD
SERIAL
QA
CONTROL
2 (L) 1 (R)
A
B
C
D
H
H
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
X
X
a
b
c
d
a
b
c
d
d
QBn
H
X
X
QCn
QDn
d
QC
QD
QB
L
L
H
X
X
X
X
X
QA0
QB0
QC0
QD0
L
X
H
X
X
X
X
H
QAn
QBn
QCn
L
X
L
X
X
X
X
L
QAn
QBn
QCn
L
L
X
X
X
X
X
QA0
QB0
QC0
QD0
X
X
X
QA0
QB0
QC0
QD0
L
L
X
X
X
X
X
QA0
QB0
QC0
QD0
L
H
X
X
X
X
X
QA0
QB0
QC0
QD0
H
L
X
X
X
X
X
QA0
QB0
QC0
QD0
H
H
X
X
+
Shifting left requires external connection of QB to A, QC to B, and QD to C.
Serial data is entered to input D.
H = High level (steady state), L = Low level (steady state),
X = Irrelevant (any input, including transitions)
= Transition from high to low level, = Transition from low to high level a, b, c,
d = the level of steady state input at inputs A, B, C, or D, respectively.
QA0, QB0, QC0, QD0 = level of QA, QB, QC, or QD, respectively,
before the indicated steady state input conditions were established.
QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD, respectively,
most recent transition of the clock.
FIGURE 2. Truth tables and timing diagrams - Continued.
17
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