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Page Title: Figure 2. Truth tables and timing diagrams Device type 04
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img
MIL-M-38510/306E
Device type 04
INPUTS
PRESET
PRESET
CLEAR
CLOCK
SERIAL
QA
QB
QC
QD
QE
ENABLE
A
B
C
D
E
L
L
X
X
X
X
X
X
X
L
L
L
L
L
L
X
L
L
L
L
L
X
X
L
L
L
L
L
H
H
H
H
H
H
H
X
X
H
H
H
H
H
H
H
L
L
L
L
L
L
X
QA0
QB0
QC0
QD0
QE0
H
H
H
L
H
L
H
L
X
H
QB0
H
QD0
H
H
L
X
X
X
X
X
L
X
QA0
QB0
QC0
QD0
QE0
H
H
QAn
H
L
X
X
X
X
X
QBn
QCn
QDn
H
L
X
X
X
X
X
L
L
QAn
QBn
QCn
QDn
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
= transition from low to high level
QA0, QB0, etc. = the level of QA, QB, etc., respectively before the indicated
steady state input conditions were established.
QAn, QBn, etc. = the level of QA, QB, etc., respectively before the most recent
transition of the clock.
Typical clear, shift, preset and shift sequences
FIGURE 2. Truth tables and timing diagrams - Continued.
18

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