a. A voltage on Pin J3-C (elevation down limit) of less than 5 Vdc
shall disable the drive ouput on Pin J4-A. Voltages between 20 and 30 Vdc on
Pin J3-C shall enable the Pin J4-A output.
b. A voltage on Pin J3-K (elevation Up limit) of less than 5 Vdc
shall cause the output current limit on Pin J4-C to be reduced to
approximately 20 percent of the normal current limit. Voltages between 20 and
30 Vdc on Pin J3-K shall produce a normal current limit on Pin J4-C.
22.214.171.124.7 Gain characteristics.
126.96.36.199.7.1 Azimuth. The azimuth input rms error signal at Pin J1-M
required to produce percent pulse width at Pin J4-F or Pin J4-D shall be
0.0005 to 0.0014 Vrms (above deadband) when the input control voltage at Pin
J3-J is 10 Vrms.
188.8.131.52.7.2 Elevation. The elevation input rms error signal at Pin J1-B
required to produce a 50 percent pulse width at Pin J4-Aor Pin J4-C shall be
0.0004 to 0.0012 Vrms (above deadband).
184.108.40.206.8 Deadband. The maximum input rms error signal required to form
on output pulse at Pins J4-A, C, D or F of the narrowest width and full
amplitude shall be as follows:
a. At J1-M (azimuth input) - 10.OmVrms
b. At J1-B (elevation input) - 8.2 mVrms
(1) Azimuth - 1.1 mVrms
(2) Elevation - l.OmVrms
Deadband shall be calculated by dividing the sum of the deadbands measured
for each polarity by two. Offset shall be calculated by dividing the
difference of the deadband measured for each polarity by two.
3.6.1 .2.9 Drive output waveform characteristics. Waveforms at Pins J4-A,
C, D, and F at a 50 percent pulse width shall have a mximum rise and fall
time of 20 s. The pulse period shall be 1.67 (+0.33) ms with the pulse width
variable from zero percent to 100 percent of the-pulse period. The amplitude
of the pulse shall be approximately 2 Vdc less than the 28 Vdc high level at
220.127.116.11.10 Velocity limit. The output voltages shall be limited as
specified in the following subparagraphs.
18.104.22.168.10.1 Azimuth limit. With 1.1 (+0.1) Vrms applied at Pin J1-M,
the drive output shall switch from one output to the other (Pins J4-D or F)
when a d-c voltage on Pin J3-R is increased from a low value to 68.75 (+10.25)
Vdc (Pin JI-M signal in phase with Pin J2-L reference) or -68.75 (±10.25) Vdc
(Pin J1 -M signal out of phase with the Pin J2-L reference voltage).