22.214.171.124.10.2 Elevation limit. With 1.1 (+0.1) Vrms applied at Pin J1-B,
the drive output shall switch from one output to the other (Pins J4-A or C)
when a d-c voltage on Pin J3-T is increased from a low voltage to 70 (+11) Vdc
or -65 Vdc (+6) Vdc. The polarity required depends on the phase of the
voltage on Pin J1-B. For a Pin J1-B signal in phase with the Pin J2-L
reference voltage, -65 (+6) Vdc is required at Pin J3-T to switch the
outputs. With an out of phase voltage on Pin J1-B, 70 (±11) Vdc is required
to switch the outputs.
126.96.36.199.11 Cross talk. When the input to PinJ1-M is such (approximately
zero mV) that no pulse width is obtained on that output (Pins J4-D or F) and
an input is applied to Pin J1-B to obtain a 50 percent pulse width output on
Pins J4-A or C, the other output (Pins J4-D or F) shall continue to produce no
pulse width output. The reverse shall occur when the input conditions of Pin
J1-B and Pin JI-M are interchanged.
188.8.131.52.12 Gun firing interrupt signals.
184.108.40.206.12.1 Azimuth. With 26.5 (+5) Vdc applied to Pin J1-K, the
voltage at pin J2-M (azmuth error gate) shall remain at 28 Vdc (1OW level)
while the input signal at Pin J1-M is increased from zero to a magnitude that
produces 1.33 Vdc (+15 percent) at Pin J2-D. With the 1.33 Vdc (+15 percent)
at Pin J2-D, the J2-M voltage shall be zero (+0.5) Vdc. When the-voltage at
pin J2-D is reduced to 1.09 Vdc (+15 percent), the voltage at pin J2-M shall
switch from zero to 28 Vdc (low level).
220.127.116.11.12.2 Elevation. With 26.5 (+5) Vdc applied to Pin J1-K, the
voltage at Pin J2-N `(elevation error gate) shall remain at 28 vdc (low level)
while the input signal at Pin J1-B is increased from zero to a magnitude that
produces 1.33 Vdc (+15 percent) at Pin J2-P. With the 1.33 Vdc (+15 percent)
at Pin J2-P. The voltage at PinJ2-N shall be zero (+0.5) Vdc. When the
voltage at Pin J2-P is reduced to 1.09 Vdc (+15 percent), the voltage at pin
J2-N shall switch from zero to 28 Vdc (low level).
18.104.22.168.13 Emergency stow mode and voltage protection. All four drive
outputs (Pins J4-A, C, D, and F) shall be disabled when any one of the following
conditions occur: (See 4.7.14).
a. The 28 Vdc (high level) at E1 is less than approximately 18 Vdc
or greater than 32 to 36 Vdc.
b. The internal -15 Vdc and +15 Vdc power supply voltages or 28 Vdc
(low level) current buss are out of tolerance.
c. The d-c voltage source at Pin J3-N is not present.
When any of the above conditions occur (except for the 28 Vdc high level
maximum condition), the voltage at Pin J3-N shall be 25.5 to 27.5 Vdc or zero
for the condition described in (c) above. Normally, the Pin J3-N voltage
shall be 2.5 to 4.0 Vdc with an external test voltage of 28 Vdc applied to Pin
J3-N through an external test circuit resistance of 10,000 ohms (±1O percent).