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3.5.1.4 Address verify. The voltage at E4 (DA) shall be 5
0.2) volts when the E11 (-CLR) is a logic one (5 0.2 volts) and
valid field set data, as specified on Drawing 9333026, has been
located when tested as specified in 4.5.2.1.5.
3.5.1.5 Hardware deploy with data transfer. When valid field
set data, as specified on Drawing 9333026, has been loaded and a
logic one is applied to E11 (-CLR) and E 9 (HWD) and a logic zero
(0 0.2 volts) is applied to E8 (-HWD), the serial data pattern at
E3 (DEP) and E6 (ADATA) shall comply with the requirements of
Figure 7. The field set data portion of the pattern in Figure 7
shall match the field set data previously loaded when tested as
specified on Drawing 9333026 when tested as specified in 4.5.2.1.6.
3.5.1.6 Hardwire deploy without data transfer. When no field
set data has been loaded and logic one is applied to E11 (-CLR)
and E9 (HWD) and a logic zero is applied to E8 (-HWD) , the serial
data pattern at E3 (DEP) and E6 (ADATA) shall comply with the
requirements of Figure 7. The field set data portion of the
pattern in Figure 7 shall be a dummy address sequence as specified
on Drawing 9333026 when tested as specified in 4.5.2.1.7.
3.5.1.7 RF link. When valid field set data has been loaded
and an RF DEPLOY command is sent via the RF link (antenna input),
as specified on Drawing 9333026, the serial data pattern at E3
(DEP) and E6 (ADATA) shall comply with the requirements of Figure
7. The field set data portion of the pattern in Figure 7 shall
match the field set data previously loaded when tested as
specified in 4.5.2.1.8.
3.5.2 Digital logic card (DLC) performance characteristics.
This section describes the performance characteristics of the
Digital Logic Card, assembly no. 9333560, a subassembly of the
Control Indicator.
3.5.2.1 Circuit continuity. Prior to making any connections
to the DLC, the DC resistance between the terminals listed below
shall be a maximum of 1 ohm when tested as specified in 4.5.2.2.1.
To
From
To
Signal
From
Signal
E10
E7
E53
VHV
J1-1
MCD1
VBT
J1-02
E9
E54
J1-14
MCD2
E20,E40,E52
E14
E25
GND
E55
L1
E14
J1-10, J1-23
E26
GND
E56
L2
E14
J1-24, J1-25
GND
J1-12
E1
DET1
E14
J1-15
GND
J1-13
E2
DET2
3.5.2.2 Regulated logic voltage. With 10.4 to 14.4 volts
applied at E9 (VBT) the output of the logic voltage regulator at
E39 (+5V) shall be 5.25 0.25 volts when tested as specified in
4.5.2.2.3.
6
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