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|  MIL-C-64030(AR)
3.5.2.3 Battery low voltage detect (LVD) threshold. The LVD
threshold shall be 1 0.7 0.3 volts when tested as specified in
4.5.2.2.4.
3.5.2.4 Lamp driver output voltage. The "ON" and "OFF"
voltages at the lamp driver outputs E12 (BTOK), E16 (CTOK), and
E15 (DALT) when connected to E9 (VBT) through a 150 ohm 2 % 2W
resistor when tested as specified in 4.5.2.2.5 shall be as listed
below.
"OFF" Voltage
Lamp Driver
"ON" Voltage
(Volts)
(volts)
output
Vbt 0.1 *
E12 (BTOK)
1.3 max
Vbt + 0.1
E16 (CTOK)
0.3 max
E15 (DALT)
0.3 max
Vbt 0.1
* Vbt is the voltage on E9 (VBT).
3.5.2.5 Fast clock output (frame sync mode). The signal on
the fast clock output, E50 (-FCL) , in the frame sync mode of
operation shall have the same frequency as the input signal on E45
(DLACK) with a low level of 0.2 + 0.2 volt and a high level of
5 0.5 volts when tested as specified in 4.5.2.2.6.
3.5.2.6 Fast clock output (deploy mode). The signal on the
fast clock output, E50 (-FCL), in the deploy mode of operation
shall be a 14.9 KHZ 10% square wave with a low level of 0.2
0.2 volt and a high level of 5 0.5 volts when tested as
specified in 4.5.2.2.7.
3.5.2.7 Electric battery initiation (EBI) waveforms. In
response to a deploy command, the tube drivers, when loaded as
shown in figure 6 (EBI configuration), shall each generate the
series of pulses shown in figure 1. The EBI waveforms shall occur
in consecutive order as specified in figure 2. The energy
transferred from the tube drivers to each 3.3 ohm EBI load
resistor shall be 2500 ergs minimum when tested as specfied in
4.5.2.2.8.1.
3.5.2.8 High voltage supply. With the voltage on E9 (VBT)
set to 13 0.5 volts, the high voltage supply output voltage at
E10 (VHV), when enabled, shall be 18.6 volts minimum and 19.5
volts maximum when tested as specified in 4.5.2.2.8.2.
3.5.2.9 Field set data (FSD) sequence. In response to a
deploy command, the tube drivers, when loaded as shown in figure 6
(FSD configuration), shall each generate the FSD sequence shown in
figure 3. The FSD sequences shall occur in consecutive order as
specified in figure 4 when tested as specified in 4.5.2.2.8.3.
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