 |
|||
|
|
|||
| ||||||||||
|
|  MIL-C-64030(AR)
3.5.2.10 Detonator driver pulses. In response to a deploy
command, the detonator driver outputs J1-12 (DET1) with respect to
J1-24 (DET1(R)) and J1-13 (DET2) with respect to J1-25 (DET2(R))
shall each generate exponentially decaying pulses which meet the
requirements of figure 5 when tested as specified in 4.5.2.2.8.4.
3.5.2.11 Accelerated arm sequence. The DLC arming sequence
can be accelerated when tested as specified in 4.5.2.2.9.
3.5.2.12 Hardwire input circuit reversed polarity. Voltage
at E47 (HWD) shall be 5 0.3 volts and the voltage at E46 (-HWD)
is 0.2 0.2 volts when tested as specified in 4.5.2.2.10.
3.5.3 Control indicator performance characteristics. This
section describes the performance characteristics of the Control
Indicator assembly no. 9333036.
3.5.3.1 Safe/arm switch resistance. The DC resistance of the
Safe/Arm Switch circuits shall be as specified below when measured
between the points listed in the table-for each of the four switch
positions: SAFE, TEST, LOAD, and ARM when tested as specified in
4.5.2.3.1.
From
To
Signal
SAFE
TEST
LOAD
ARM
<1
DET1
J1-12
J1-24
> 1K
<1
> 1K
<1
<1
DET2
J1-13
J1-25
> 1K
> 1K
*
<1
A1A2E10
VHV
J1-23
51 5
<1
*
*
<1
L1
J1-23
A1A2E25
<1
*
*
L2
A1A2E26
J1-23
<1
<1
**
*
*
*
GND
A1A2E20
<1
* Do not measure
** An exposed area of the control indicator casting
3.5.3.2 Quiescent current. With the voltage at E6 (+14.4 VDC)
with respect to ES (COMMON) set to 13 0.5 volts, the current
flowing into E6 (+14.4 VDC) shall be 16 milliamperes maximum when
tested as specified in 4.5.2.3.8.
3.5.3.3 Electric battery initiation (EBI) waveforms. In
response to a HARDWIRE DEPLOY or RF DEPLOY command, the tube
drivers shall each generate the series of pulses such as the EBI
burst and sequence shown in figure 1 and 2. The total energy
transferred from the tube drivers to each 3.3 ohm EBI load
resistor, as the result of the series of pulses, shall be 2500
ergs minimum when tested as specified in 4.5.2.3.10.1.
3.5.3.4 Field set data (FSD) sequence. In response to a
HARDWIRE DEPLOY or RF DEPLOY command, the tube drivers shall each
generate the FSD sequence shown in figure 3. This sequence shall
be generated at each of the tube driver outputs in consecutive
order meeting the requirements of figure 4 when tested as
8
|
|
Privacy Statement - Press Release - Copyright Information. - Contact Us |
Click
here for thousands of PDF manuals