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|  MIL-D-81347C(AS)
3.5.4.4.4.3.3.4.7.4
Track selection - The MDM shall include logic to decode the
binary address and select one track for writing on or reading from the drum.
Track Switching - When the track address is changed from one
3.5.4.4.4.3.3.4.7.5
track to another track, the new track shall be selected in less than eight word times of the time that
the new address is sent to the MDM.
Track Error - The MDM shall provide a Logic 1 level to the
3.5.4.4.4.3.3.4.7.6
Drum Controller whenever a track address change is made and any of the conditions listed below is
detected.
(1) No track selection
(2) More than one track selected
(3) A track address greater than 384 selected
The track error signal shall assume its proper state no later
than two word times after a track address change has been made by the Drum Controller.
This signal is defined as the MDM track error status signal.
Drum Clocks - Unless otherwise specified the MDM shall contain
3.5.4.4.4.3.3.4.8
and provide clock signals to the drum controller as defined in the following paragraphs.
Bit Clock Selection - The MDM shall contain two bit clock tracks
3.5.4.4.4.3.3.4.8.1
either of which is selectable by means of an external switch. It shall be possible to read data written
by one of the two clocks by using either the original writing clock or the other clock. Specified opera-
tion is not required if the position of the clock select switch is changed during a read, write or test
mode operation.
Bit Clock - The bit clock shall be supplied to the Drum Con-
3.5.4.4.4.3.3.4.8.2
troller via the Bit Clk Tst Line and shall be under control of the MDM Track Test Inhibit line. When-
ever a Logic 1 level is detected on the MDM Track Test Inhibit line, the MDM shall automatically
inhibit bit clocks on the Bit Clk Tst line and provide a Logic O level to the Drum Controller. Upon de-
tection of an open-circuit condition on the MDM Track Test Inhibit line, the MDM shall automatically
provide bit clocks to the Drum Controller on the Bit Clk Tst line. The bit clocks supplied by the MDM
shall have a pulse width of 156 50 nanoseconds and a period of 312.8 l 53 nanoseconds.
Tachometer Clock - The tachometer clock shall be supplied to
3.5.4.4.4.3.3.4.8.3
the Drum Controller and shall consist of one pulse to a Logic 1 state per drum revolution. Pulse width
shall be as indicated in the continuous clock timing diagram, Figure 155.
Word Clock - The word clock shall be derived from one of the
3.5.4.4.4.3.3.4.8.4
recorded bit clocks and it shall be transmitted to the Drum Controller. There shall be 1249 word
clock pulses per drum revolution which have pulse widths and time relationships to each other and to
the tachometer clock pulses as shown in the continuous clock signal timing diagram, Figure 155.
Byte Clock - Data shall be transmitted between the MDM and the
3.5.4.4.4.3.3.4.8.5
Drum Controller in four 8-bit bytes per word transmitted. The MDM shall send a byte clock to the
Drum Controller with which the data bytes are synchronized. The time relationships between the byte
clock and word clock or sector begin pulse shall be as defined in the write operation sequence, read
operation sequence, MDM Test Mode 1 and MDM Test Mode 2 paragraphs of the MDM section of this
specification.
Clock Error - The MDM shall have the capability of detecting
3.5.4.4.4.3.3.4.8.6
a bit clock timing error. when an error is detected, a Logic 1 level signal shall be sent to the Drum
Controller via the MDM Clock Error Status line. The minimum duration of this signal shall be two
word times and the maximum shall be 1251 word times after the bit clock returns to normal. The
MDM shall inhibit writing when a clock error is detected.
272
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