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|  MIL-D-81347C(AS)
Clock Retention - During continuous drum operation or power
3.5.4.4.4.3.3.4.8.7
on/power off cycling, the tachometer and bit clock shall not exhibit any deterioration effects such that
write and/or read operations with the drum cannot be performed within the specified MDM error rate.
W r i t e / O p e r a t i o n s - The MDM shall perform data writing
3.5.4.4.4.3.3.4.9
and reading as defined in the following paragraphs.
W r i t e Operation Sequence - The write operation sequence timing
3.5.4.4.4.3.3.4.9.1
is shown in the write operation timing diagram, Figure 156 and is described as follows:
(1) The write command signal becomes a Logic 1 at least eight
word times prior to the actual initiation of writing and remains in that state.
(2) At
the proper time a sector begin pulse is sent to the MDM.
This pulse will be coincident with one of the
word clock pulses, except for the effects of logic circuit
time delays. When this pulse is received the
MDM shall write the sector preamble word in the word
space immediately following the sector begin
pulse.
(3) The MDM shall, at the time that data words are needed,
send byte clock pulses to the Drum Controller. The sectors may contain any number of data words
greater than or equal to one. Each data word shall be sent to the MDM in four bytes of eight bits each.
The data shall be recorded serially on the specified track using one word clock time per data word
recorded. The number of byte clock pulses sent to the Drum Controller shall be some multiple of four.
(4) When the last data word of the sector has been received by
the MDM, the Drum Controller shall send a sector end pulse after which the MDM shall cease sending
byte clock pulses and terminate the write operation after the last byte has been written. Write current
to the write head shall be "turned on" upon receipt of the sector begin pulse from the controller and
automatically "turned off" after the last bit of the last byte of data has been written on the drum. The
last word of a data sector shall be written in a position such that the preamble word for the next sector
may be written in the next word space during either this same or any subsequent drum revolution by
means of another sector begin pulse.
(5) As the data bytes are being written the MDM shall per-
form a serial parity check on the data. Each word of data is sent in a four byte sequence designated
bytes 1, 2, 3, and 4 respectively. The combination of bytes 1 and 2 shall be checked for odd parity
and a parity error shall be indicated by a pulse on the Byte 1/2 Parity Error line. The combination of
bytes 3 and 4 shall be checked for odd parity and a parity error shall be indicated by a pulse on the
Byte 3/4 Parity Error line.
(6) When a track switch is necessary, the track address state
is changed at least eight word clock pulses prior to the time that a sector begin pulse is sent to the
MDM. At no time shall a track switch occur within a sector.
Read Operation Sequence - The read operation sequence timing
3.5.4.4.4.3.3.4.9.2
is shown in the read operation timing diagram, Figure 157 , and is described as follows:
(1) The read command signal becomes a Logic 1 at least eight
word times prior to the actual initiation of reading and remains in that state.
(2) At the proper time, a sector begin pulse is sent to the
MDM. This pulse shall be coincident with one of the word clock pulses, except for the effect of logic
circuit time delays. When this pulse is received the MDM shall start reading on the specified track
the preamble word which should have been written in the word space immediately following the sector
begin pulse. If the preamble word is not detected the Controller shall terminate the instruction by a
Logic O on the Read Command line.
(3) When the preamble word is detected the MDM shall send a
pulse on the Preamble Detect line and initiate the reading of the data. The data shall be read and
formatted into eight-bit bytes just as it was received when written. The data transmission to the Drum
273
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