 |
|||
|
Page Title:
TM-7 Address Logic and Error Address Counter |
|
||
| ||||||||||
|
|  MIL-D-81347C(AS)
Upon completion of the buffer loading, a 64 IDR/IA input
sequence shall be initiated through the normal data paths. Any parity error detected during buffer
unloading to the computer shall increment the buffer error, byte error and overrun/underrun counters.
Upon detection of a parity error, with output bit 21 of the TM-5 instruction word a logic 1, the buffer
error strobe shall precede the byte error strobe; with output 21 of the TM-5 instruction word a logic O,
the byte error strobe shall precede the buffer error strobe.
Upon completion of the input data transfer, the instruction status
word shall be sent to the computer via the EI/IA sequence. Any parity error detected shall set the
parity error bit (bit 28) of the instruction status word. A computer initiated parity status and/or error
count instruction shall be used to verify parity status bits and error count data.
Several TM-5 sequences shall be initiated to accumulate and
verify full count of the error count registers. The error count data shall not be reset until a master
clear, write/read instruction or any test instruction other than TM-5 is received.
(6) TM-6 Drum Fault Status Bits - This test mode shall exer-
cise and verify the drum fault status register operation. TM- 6 shall verify DAMS status logic and
data paths from the status registers to the computer.
Test mode entry shall be via the EFR/EF. The DAMS shall then
raise the ODR to the computer. The computer shall respond with an OA word, the contents of which
shall determine which of the register bits and drum fault indicators shall be set. If any or all of the
OA word O0B09-04 is a logic 1, the corresponding status register bits shall be sent and the respective
IB09-04 of the instruction status word shall indicate a drum fault. 0B03-00 of the OA word shall be
used to test IB10 of the instruction status word.
Upon receipt of the OA, the DAMS shall raise the EI, enabling
the instruction status word to the computer.
(7) TM-7 Address Logic and Error Address Counter - This
test mode shall allow operational verification of the address counters, word counter, address com-
parators and parity error address counter. This shall be accomplished by using the byte error
counter as a burst clock generator to increment the registers and counters.
Test mode entry shall require a two word EFR/EF sequence and
one ODR/OA sequence:
The first word shall load the computer and drum
(a)
begin address registers and parity error address register.
(b) The second word shall load the instruction end
address and word address counters. The status of bits 20 and 21 shall determine where the burst
clocks are applied. Bit 20 shall inhibit or enable the burst clocks to the computer begin address and
drum begin address registers. Bit 21 shall inhibit or enable the burst clocks to the instruction end
address register and the track word address counter.
(c) The OA word shall load the byte error counter and
determine the number of burst clocks to be generated.
Upon receipt of the OA, the byte error counter shall be enabled
generating the predetermined number of burst clocks to increment the registers and counters. When
the error counter is full, the DAMS shall raise the IDR, which shall result in the address comparator
diagnostic data being supplied to the computer via the enabled data path. As the computer IA acknowl-
edge is received, the DAMS shall send the parity status word to the computer via the EI/IA sequence
for parity error address verification.
(8) TM-8 Control Logic - This test mode shall provide the
capability for checking certain control signals within the DAMS not tested by the other DAMS test modes.
The test shall be initiated by means of an instruction word from the computer using EFR/EF control
sequent e. This word shall cause entry into the test mode and shall determine the behavior of the sig-
nals under test.
286
|
|
Privacy Statement - Press Release - Copyright Information. - Contact Us |
Click
here for thousands of PDF manuals