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|  MIL-F-48673 (AR)
Computer phases" "are Utilized" to control" Memory
be Phases.
"
and Display.
c. ZC Bus. 16 bit interval CPU bus, switches at computer
clock rate of 3.36 MHz, carries output address during output
instruction execution and memory references.
d. INSTR Lines. INSTR Lines are decoded to load display
data and 1/0 start condition.
Test Set shall provide as inputs to
3.2.2.2 FCC input signals.
the FCC the following:
12 bits of code from the TEST SELECT switches and MODE
a.
switches.
Simulated serial 1/0 signals (Air Data Subsystem and
b.
Doppler).
3.2.2.3 Test points interface signals. The following signals
are to be available at the test points:
. 3.36 MHz CPU logic clock
CLOCK
CPU Phase (state) counter, time reference
PHAr PHB, PHC
for ZB and ZC register monitor
- Instruction Lines
I NSTR
- Real Time Interrupt Override
RINTO
- Power supply sequencing output
ON
Memory Cycle Initiate Pulse
MC INT
- CPU bus control lines
MCS, CLD
- Programmed clock stop command
HALT
1/0 SIGNALS
+ 15v, +5.5v +5 VDc
Power supply
voltage monitors
3.2.2.4 Test points. Jacks to observe test points in the event
that the FCC processor is so disabled that it cannot execute any
programs at all. These test points shall include:
All power supply output voltages.
a.
Basic system timing - logic and real time clocks.
b.
c. Critical control functions - memory cycle initiate,
memory mode, and power SUpplY logic sequencing signals.
Ground returns.
d.
4
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