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|  MIL-I-48331A(AR)
3 .14.6 "1" output voltage: terminals 13 (Initiator) and
The IC, when connected as shown in fig. 10,
15 (Detonator).
shall meet the requirements of Tables II, III & IV.
3.14.7 "0" output voltage: terminals 13 (Initiator) and
The IC, when connected as shown in fig. 11,
15 (Detonator).
shall meet the requirements of Tables II, III & IV.
3.14.8 Input switching voltage, terminals 2 (F1) and 10
(F2). See fig. 14. A slowly increasing voltage is applied to
terminal 2 or 10. The level on pin 1 or 9 shall be observed
and when pin 1 or 9 goes from a low to a high level, the
voltage level on terminal 2 or 10 shall be measured as the
threshold voltage on pin 2 or 10.
3.14.9 Sequential operation. The IC, when connected as
shown in fig. 5 and the waveforms shown in fig. 6 are applied
to terminals 1, 2, 4, 5, 6, 7, 16, 9, 10 and 14, shall operate
as described by the output waveforms in fig. 7.
3.14.10 Sequential operation waveform characteristics.
All pulse magnitudes (figures 6 and 7) are equal to VDD except
on pin 4 as shown on figure 6 and explained i n 3.2.7.11. Al l
pulse counts are referenced to the zero start time. One pulse
count is equal to one pulse of the oscillator (terminals 1 and
2).
3.14.11 Input terminal number four (4) (LVD). The input
voltage levels applied to the input terminal number four (4)
during the sequence test must be the maximum and minimum LVD
voltages specified in Table II. See fig. 13.
3.14.12 Input resistance. The input resistance on
terminals 5,6, and 7 shall be measured by connecting the device
as shown in fig. 15 and meet the requirement in Table II.
3.14.13 "1" output voltage: terminal 1, 3 (F1), 9 and 11
(F2). The IC, when connected as shown in fig. 16, shall meet
the requirements of Table II.
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