Modules, Standard Electronic. Gate, NAND, Digital, Key Code BDC

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Modules, Standard Electronic. Gate, NAND, Digital, Key Code BDC

Modules, Standard Electronic. Gate, NAND, Digital, Key Code BDC
Module Configuration Requirements
Alternate Test Methods
Figure 1. BDC function diagram, NAND gate
Table I. Module electrical requirements
Table I. Module electrical requirements (Cont)
Module Description
Table II. Input to output relationship foreach NAND gate
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Table III. Zener applied potential test
Table III. Zener applied potential test (cont)
Figure 5. Zener applied potential test circuit for table III
Figure 5. Zener applied potential test circuit for table III (cont)
Figure 6. Zener applied potential test circuit waveform for table III
Table IV. VOUT (low-loaded) test
Figure 7. VOUT (low-loaded) test circuit for table IV
Table V. Isolation and continuity test
Figure 4. Isolation and continuity test circuit for table V
Table VI. Output voltage (high-level and low-level) test
Table VI. Output voltage (high-level and low-level) test (cont)
Table VI. Output voltage (high-level and low-level) test (cont)
Figure 9. Output voltage (high-level and low-level) test circuit for table VI
Table VII. Output short circuit current test
Table VIII. Input current (low-level and high-level) test
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Figure 10. Output short circuit current and Input current (low-level and high-level) test circuit
Table IX. Input capacitance test
Table IX. Input capacitance test (cont)
Figure 11. Input capacitance test circuit for table IX
Table X. Power supply current (high-level and low-level) test
Figure 12. Power supply current (high-level and low-level) test circuit for table X
Table XI. Power supply transient rise time test
Figure 13. Power supply transient rise time test circuit for table XI
Figure 14. Power supply transient rise time test circuit waveforms for table XI
Table XII. Output pulse amplitude (high-level and low-level) test
Table XIII. Transition time (tTHL and tTLH) and Propagation delay time (tPLH and tPHL) test
Figure 15. Output pulse amplitude, transition time and propagation delay time test circuit for tables XII and XIII
Figure 16. Output pulse amplitude, transition time and propagation delay time test circuit waveforms
Figure 17. BDC Logic load circuit
Tabel XIV. Output crosstalk (high-level and low-level) test
Figure 18. Output crosstalk (high-level and low-level) test circuit for tabl;e XIV
Figure 19. Output crosstalk (high-level and low-level) test circuit waveforms for table XIV
Standardization Document Improvement Proposal
Address

Modules, Standard Electronic. Gate, NAND, Digital, Key Code BDC

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