Modules, Standard Electronic Gate, NAND, Digital, Key Code LDN

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Modules, Standard Electronic Gate, NAND, Digital, Key Code LDN

Modules, Standard Electronic Gate, NAND, Digital, Key Code LDN
Failure Rate Requirements
Figure 1. LDN module function diagram, NAND gate
Table I. Module electrical requirements
Table I. Module electrical requirements (Cont)
Vibration Tests
Table II. Input to output relationship
Changes from Previous Issue
Figure 2. Operating temperature, life and burn-in test circuit
Figure 3. Component test circuit
Figure 4. Vibration test circuit
Table III. V out (low-loaded) test
Figure 5. V out (low-loaded) test circuit for table III
Table IV. Input breakdown current test
Table IV. Input breakdown current test (cont)
Figure 6. Input breakdown current test circuit for table IV
Table V. Input clamp diode voltage test
Table V. Input clamp diode voltage test (cont)
Figure 7. Input clamp diode voltage test circuit for table V
Table VI. Output voltage (low-level) test
Table VIII. Output voltage (high-level) test
Table VIII. Output voltage (high-level) test (cont)
Figure 8. Output voltage (low-level and high-level) test circuit for tables VI and VII
Figure 9. Logic load circuit
Table VIII. Input current (low-level) test
Table VIII. Input current (low-level) test (cont)
Table IX. Input current (high-level) test
Table IX. Input current (high-level) test (cont)
Table X. Output short circuit current test
Figure 10. Input current (low-level and high-level) and output short circuit current test circuit
Figure 11. Power supply current (low-level and high-level) test circuit for table XI
Table XII. Transition time (tTLH and tTHL) test
Table XIII. Propagation delay time (tPHL and tPLH) test
Figure 12. Transition time (tTLH and tTHL) and Propagation delay time (tPHL and tPLH) test circuit
Figure 12. Transition time (tTLH and tTHL) and Propagation delay time (tPHL and tPLH) test circuit waveforms
Table XIV. Output crosstalk (low-level) test
Table XV. Output crosstalk (high-level) test
Figure 14. Output crosstalk (high-level and low-level) test circuit for tables XIV and XV
Figure 14. Output crosstalk (high-level and low-level) test circuit waveforms for tables XIV and XV
Table XVI. Power supply transient amplitude test
Figure 16. Power supply transient amplitude test circuit for table XVI
Figure 17. Power supply transient amplitude test circuit waveforms for table XVI
Figure 18. Power supply transient rise time test circuit for table XVII
Figure 19. Power supply transient rise time test circuit waveforms for table XVII
Figure 20. Isolation test circuit for table XVIII
Table XIX. Input capacitance test
Table XIX. Input capacitance test (Cont)
Figure 21. Input capacitance test circuit for table XIX
Amendment Forms
Address
Standardization Document Improvement Proposal

Modules, Standard Electronic Gate, NAND, Digital, Key Code LDN

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