Modules, Standard Electronic, Standard Serial Output, Digital, Key Code DQD

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Modules, Standard Electronic, Standard Serial Output, Digital, Key Code DQD

Modules, Standard Electronic, Standard Serial Output, Digital, Key Code DQD
Failure Rate Requirements
Quality Assurance Provisions
Figure 1. DQD module function diagram, standard serial output
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Packaging Requirements
Module Description
Module Description (cont)
Module Function
Clocks and Strobes
Test Point Jumpers
Pin Nomenclature
Parallel Outputs
Figure 2. Broadcast (mode timing)
Figure 3. Broadcast
Figure 4. Controlled serial mode timing
Table II. Counter pin programming (SSOE)
Table II. Counter pin programming (SSOE) (cont)
Table II. Counter pin programming (SSOE) (cont)
Table II. Counter pin programming (SSOE) (cont)
Table II. Counter pin programming (SSOE) (cont)
Table II. Counter pin programming (SSOE) (cont)
Changes from Previous Issue
Figure 5. Operating temperature and life test circuit
Figure 6. Operating temperature and life test circuit waveform
Figure 7. Component temperature test circuit
Figure 8. Vibration test circuit
Table II. Isolation test
Figure 9. Isolation test circuit for table III
Table IV. VOUT (low-loaded) test
Figure 10. VOUT (low-loaded) test circuit for table Iv
Table V. Input breakdown current test
Table V. Input breakdown current test (Cont)
Figure 11. Input breakdown current test circuit for table V
Table VI. Output short circuit current test
Figure 12. Output short circuit current test circuit for table VI
Table VII. Functional test
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Table VII. Functional test (cont)
Figure 13. Functional test circuit for table VII
Table VIII. Input clamp diode voltage test
Table VIII. Input clamp diode voltage test (cont)
Figure 14. Input clamp diode voltage test circuit for table VIII
Table IX. Static Output voltage (low-level) test
Table IX. Static Output voltage (low-level) test (Cont)
Table X. Static Output voltage (high-level) test
Figure 15. Static Output voltage (low-level and high-level) test circuit for tables IX and X
Figure 16. DQD logic load circuit
Table XI. Input current (high-level) test
Table XI. Input current (high-level) test (cont)
Figure 17. Input current (high-level) test circuit for table XI
Table XII. Input current (low-level) test
Table XII. Input current (low-level) test (cont)
Figure 18. Input current (low-level) test circuit for table XII
Table XIII. Power supply current test
Figure 19. Power supply current test circuit for table XIII
Table XIV. Transition time (tTLH) test
Table XIV. Transition time (tTLH) test (cont)
Table XIV. Transition time (tTLH) test (cont)
Table XV. Transition time (tTHL) test
Table XV. Transition time (tTHL) test (cont)
Table XV. Transition time (tTHL) test (cont)
Figure 20. Transition time (tTLH and tTHL) test circuit for tables XIV and XV
Figure 21. Transition time (tTLH and tTHL) test circuit waveforms for tables XIV and XV
Table XVI. Propagation delay time (tPLH) test
Table XVII. Propagation delay time (tPHL) test
Figure 22. Propagation delay time (tPLH and tPHL) test circuit for tables XVI and XVII
Figure 23. Propagation delay time (tPLH and tPHL) test circuit waveforms for tables XVI and XVII
Figure 23. Propagation delay time (tPLH and tPHL) test circuit waveforms for tables XVI and XVII (cont)
Table XVIII. Skew, spike width, and pulse width test
Figure 24. Skew, spike width, and pulse width test circuit for table XVIII
Figure 24. Skew, spike width, and pulse width test circuit for table XVIII (Cont)
Figure 25. Skew, spike width, and pulse width test circuit waveforms for table XVIII
Figure 26. Skew, spike width, and pulse width test circuit waveforms for table XVIII
Table XIX. Output crosstalk (high-level) test
Table XX. Output crosstalk (low-level) test
Table XX. Output crosstalk (low-level) test (cont)
Figure 27. Output crosstalk (high-level and low-level) test circuit for tables XIX and XX
Figure 28. Output crosstalk (high-level and low-level) test circuit waveforms for tables XIX and XX
Table XXI. Power supply transient amplitude test
Figure 29. Power supply transient amplitude test circuit for table XXI
Figure 30. Power supply transient amplitude test circuit waveforms for table XXI
Table XXII. Input capacitance test
Table XXII. Input capacitance test (cont)
Table XXIII. Power supply filter capacitance test
Figure 31. Input and power supply filter capacitance test circuit for tables XXII and XXIII
Standardization Document Improvement Proposal
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Modules, Standard Electronic, Standard Serial Output, Digital, Key Code DQD

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