Modules, Standard Electronic, Counter, Binary, Digital, Key Code AMF

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Modules, Standard Electronic, Counter, Binary, Digital, Key Code AMF

Modules, Standard Electronic, Counter, Binary, Digital, Key Code AMF
Module Configuration Requirements
Figure 1. AMF module function digram, binary counter
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Alternate Test Methods
Module Description
Input to Output Relationship
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Table III. Isolation test
Figure 5. Isolation test circuit for table III
Table IV. Input clamp diode voltage (negative) test
Figure 6. Input clamp diode voltage (negative and positive) test circuit for tables IV and V
Table VI. Functional test
Figure 7. Functional test circuit for table VI
Figure 8. Functional test circuit waveforms for table VI
Table VII. Static output voltage (low-level) test
Figure 9. Static output voltage (low-level) test circuit for table VII
Table VIII. Static output voltage (high-level) test
Figure 10. Static output voltage (high-level) test circuit for table VIII
Figure 11. Static output voltage (high-level) test circuit waveforms for table VIII
Table IX. Static output voltage (low-level, VDD = 5 V) test
Figure 12. Static output voltage (low-level, VDD = 5.0 V) test circuit for table IX
Table X. Static output voltage (high-level, VDD = 5 V) test
Figure 13. Static output voltage (high-level, VDD = 5 V) test circuit for table X
Figure 14. Static output voltage (high-level, VDD = 5 V) test circuit waveform for table X
Table XI. Static output voltage (low-level, VDD = 15 V) test
Table XII. Static output voltage (high-level, VDD = 15 V) test
Figure 15. Static output voltage (low-level, VDD = 15 V) test circuit for tables XI and XII
Figure 16. Static output voltage (low-level and high-level, VDD = 15 V) test circuit waveform for tables XI and XII
Table XIII. Input current (low-level) test
Figure 17. Input current (low-level) test circuit for table XIII
Table XIV. Input current (high-level) test
Figure 18. Input current (high-level) test circuit for table XIV
Table XV. Power supply current (low-level and high-level) test
Figure 19. Power supply current (low-level and high-level) test circuit for table XV
Figure 20. Power supply current (low-level and high-level) test circuit waveform for table XV
Table XVI. Transition time (tTLH) test
Table XVII. Transition time (tTHL) test
Table XVIII. Transition time (tTLH) test
Table XIX. Transition time (tTHL) test
Table XX. Transition time (tTLH) test
Table XXI. Transition time (tTHL) test
Table XXII. Propagation delay time (tPLH) test
Table XXIII. Propagation delay time (tPHL) test
Table XXIV. Propagation delay time (tPLH) test
Table XXV. Propagation delay time (tPHL) test
Table XXVI. Propagation delay time (tPLH) test
Table XXVII. Propagation delay time (tPHL) test
Figure 21. Transition time (tTLH and tTHL) and Propagation delay time (tPLH and tPHL) test circuit
Figure 22. Transition time (tTLH and tTHL) and Propagation delay time (tPLH and tPHL) test circuit waveforms
Figure 22. Transition time (tTLH and tTHL) and Propagation delay time (tPLH and tPHL) test circuit waveforms(cont)
Table XXVIII. Propagation delay time (tPHL) test
Table XXVIII. Propagation delay time (tPHL) test (cont)
Table XXIX. Propagation delay time (tPHL) test
Table XXX. Propagation delay time (tPHL) test
Figure 23. Propagation delay time (tPHL) test circuit for tables XXVIII, XXIX and XXX
Figure 24. Propagation delay time (tPHL) test circuit waveforms for tables XXVIII, XXIX and XXX
Figure 24. Propagation delay time (tPHL) test circuit waveforms for tables XXVIII, XXIX and XXX (cont)
Table XXXI. Minimum reset pulse width check test
Figure 25. Minimum reset pulse width check test circuit for table XXXI
Figure 26. Minimum reset pulse width check test circuit waveforms for table XXXI
Table XXXII. Maximum clock frequency check test
Figure 27. Maximum clock frequency check test circuit for table XXXII
Figure 28. Maximum clock frequency check test circuit waveforms for table XXXII
Table XXXIII. Power supply filter capacitance test
Table XXXIV. Capacitance (C1 and C2) test
Table XXXV. Input capacitance test
Figure 29. Power supply filter capacitance, capacitance (C1 and C2) and input capacitance test circuit
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Modules, Standard Electronic, Counter, Binary, Digital, Key Code AMF

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