Modules, Standard Electronic, Buffer, Bidirectional, Digital, Key Code HRL

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Modules, Standard Electronic, Buffer, Bidirectional, Digital, Key Code HRL

Modules, Standard Electronic, Buffer, Bidirectional, Digital, Key Code HRL
Failure Rate Requirements
Figure 1. HRL module function diagram, bidirectional buffer
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Qualification Testing
Module Function
Table II. Input to output relationship
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Table III. Isolation test
Figure 5. Isolation test circuit for table III
Figure 6. Vcc maximum stress test circuit for table IV
Table V. Output short circuit current test
Table V. Output short circuit current test (cont)
Figure 7. Output short circuit current test circuit for table V
Table VI. Input clamp diode voltage test
Table VI. Input clamp diode voltage test (cont)
Figure 8. Input clamp diode voltage test circuit for table VI
Table VII. Output leakage current (high-level) test
Table VII. Output leakage current (high-level) test (cont)
Table VII. Output leakage current (high-level) test (cont)
Table VII. Output leakage current (high-level) test (cont)
Table VII. Output leakage current (high-level) test (cont)
Table VIII. Output leakage current (power-off) test
Figure 9. Output leakage current (high-level and power-off) test circuit for tables VII and VIII
Table IX. Output leakage current (low-level) test
Table IX. Output leakage current (low-level) test (cont)
Table IX. Output leakage current (low-level) test (cont)
Table IX. Output leakage current (low-level) test (cont)
Table IX. Output leakage current (low-level) test (cont)
Figure 10. Output leakage current (low-level) test circuit for table IX
Table X. Output voltage (low-level) test
Table X. Output voltage (low-level) test (cont)
Table X. Output voltage (low-level) test (cont)
Table X. Output voltage (low-level) test (cont)
Table XI. Output voltage (high-level) test
Table XI. Output voltage (high-level) test (cont)
Table XI. Output voltage (high-level) test (cont)
Figure 11. Output voltage (low-level and high-level) test circuit for tables X and XI
Figure 12. Output voltage (low-level) test circuit for tables X
Figure 13. HRL logic load circuit for "A" outputs
Figure 14. HRL logic load circuit for "B" outputs
Table XII. Input current (high-level) test
Figure 15. Input current (high-level) test circuit for table XII
Figure 16. Input current (low-level) test circuit for table XIII
Table XIV. Power supply current test
Figure 17. Power supply current test circuit for table XIV
Table XV. Transition time (tTLH) test
Table XV. Transition time (tTLH) test (cont)
Table XVI. Transition time (tTHL) test
Table XVI. Transition time (tTHL) test (cont)
Table XVII. Propagation delay time (tPLH) test
Table XVII. Propagation delay time (tPLH) test (cont)
Table XVII. Propagation delay time (tPLH) test (cont)
Table XVIII. Propagation delay time (tPHL) test
Table XVIII. Propagation delay time (tPHL) test (cont)
Table XVIII. Propagation delay time (tPHL) test (cont)
Figure 18. Transition time (tTLH and tTHL) and propagation delay time (tPLH and tPHL) test circuit
Figure 19. Transition time (tTLH and tTHL) and propagation delay time (tPLH and tPHL) test circuit waveforms
Table XIX. Output disable delay time (tOH) test
Table XIX. Output disable delay time (tOH) test (cont)
Table XX. Output disable delay time (tH0) test
Table XX. Output disable delay time (tH0) test (Cont)
Table XXI. Output disable delay time (t1H) test
Table XXI. Output disable delay time (t1H) test (cont)
Table XXII. Output disable delay time (tH1) test
Table XXII. Output disable delay time (tH1) test (cont)
Figure 20. Output disable delay time (t0H, tH0, t1H, tH1) test circuit for tables XIX, XX, XXI and XXII
Figure 21. Output disable delay time (t0H, tH0, t1H, tH1) test circuit waveforms
Table XXIII. Output crosstalk (low-level) test
Table XXIII. Output crosstalk (low-level) test (cont)
Table XXIII. Output crosstalk (low-level) test (cont)
Table XXIV. Output crosstalk (high-level) test
Table XXIV. Output crosstalk (high-level) test (cont)
Table XXIV. Output crosstalk (high-level) test (cont)
Figure 22. Output crosstalk (low-level and high-level) test circuit for tables XXIII and XXIV
Figure 23. Output crosstalk (low-level and high-level) test circuit waveforms for tables XXIII and XXIV
Table XXV. Power supply transient amplitude test
Figure 24. Power supply transient amplitude test circuit for table XXV
Figure 25. Power supply transient amplitude test circuit waveforms for table XXV
Table XXVII. Input capacitance test
Table XXVII. Input capacitance test (cont)
Figure 26. Power supply filter and input capacitance circuit for table XXVI and XXVII
Standardization Document Improvement Proposal
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Modules, Standard Electronic, Buffer, Bidirectional, Digital, Key Code HRL

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