Modules, Standard Electronic, Flip-Flop, D-Type, Digital, Key Code KBR

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Modules, Standard Electronic, Flip-Flop, D-Type, Digital, Key Code KBR

Modules, Standard Electronic, Flip-Flop, D-Type, Digital, Key Code KBR
Failure Rate Requirements
Figure 1. Module function diagram, D type flip-flop
Table I. Module electrical requirements
Table I. Module electrical requirements (Cont)
Transient Thermal Test
Module Description
Table II. Input to output relationship
Figure 2. Operating temperature and life test circuit
Figure 3. Transient Thermal Test Circuit
Figure 4. Vibration test circuit
Table III. V out (low-loaded) test
Figure 5. V out (low-loaded) test circuit for table III
Table IV. Input breakdown current test
Figure 6. Input breakdown current test circuit for table IV
Table V. Isolation test
Figure 7. Isolation test circuit for table V
Table VI. Input capacitance test
Figure 8. Input capacitance test circuit for table VI
Table VII. Static Output voltage (low-level and high-level) test
Table VII. Static Output voltage (low-level and high-level) test (cont)
Table VII. Static Output voltage (low-level and high-level) test (cont)
Table VII. Static Output voltage (low-level and high-level) test (cont)
Figure 9. Static Output voltage (low-level and high-level) test circuit for table VII
Figure 9. Static Output voltage (low-level and high-level) test circuit for table VII (cont)
Figure 10. Logic load circuit
Table VIII. Input current (low-level) test
Table IX. Input current (high-level) test
Table IX. Input current (high-level) test (Cont)
Table X. Output short circuit current test
Figure 11. Input current (low-level and high-level) and output short circuit current test circuit
Figure 11. Input current (low-level and high-level) and output short circuit current test circuit (cont)
Table XI. Power supply current (low-level and high-level) test
Figure 12. Power supply current (low-level and high-level) test circuit for table XI
Table XII. Transition time (tTLH) test
Table XII. Transition time (tTLH) test (cont)
Table XIII. Transition time (tTHL) test
Table XIV. Propagation delay time (tPHL) (clock-to-output) test
Table XIV. Propagation delay time (tPHL) (clock-to-output) test (cont)
Table XV. Propagation delay time (tPLH) (clock-to-output) test
Table XV. Propagation delay time (tPLH) (clock-to-output) test (cont)
Table XVI. Data setup time (maximum clock frequency, minimum clock pulse width) check test
Table XVII. Data hold time check test
Figure 13. Transition time, propagation delay time, data setup time check, and data hold time check test circuit
Figure 14. Transition time, propagation delay time, data setup time check, and data hold time check - waveforms
Figure 14. Transition time, propagation delay time, data setup time check, and data hold time check - waveforms (Cont)
Table XVIII. Output crosstalk (high-level and low-level) test
Table XVIII. Output crosstalk (high-level and low-level) test (cont)
Table XIX. Power supply transient amplitude test
Figure 15. Output crosstalk (high-level and low-level) and Power supply transient amplitude test circuit
Figure 16. Output crosstalk (high-level and low-level) test circuit waveforms for table XVIII
Figure 17. Power supply transient amplitude test circuit waveforms for table XIX
Table XX. Propagation delay time (tPHL) (set- and reset-to-output) test
Table XXI. Propagation delay time (tPLH) (set- and reset-to-output) test
Figure 18. Propagation delay time (tPHL and tPLH) (set- and reset-to-output) test circuit for tables XX and XXI
Figure 19. Propagation delay time (tPHL and tPLH) (set- and reset-to-output) test circuit waveforms
Table XXII. Power supply filter capacitance test
Figure 20. Power supply filter capacitance test circuit for table XXII
Standardization Document Improvement Proposal
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Modules, Standard Electronic, Flip-Flop, D-Type, Digital, Key Code KBR

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