Modules, Digital, Standard Electronic, Clock, Microprocessor Module, Key Code TRU

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Modules, Digital, Standard Electronic, Clock, Microprocessor Module, Key Code TRU

Modules, Digital, Standard Electronic, Clock, Microprocessor Module, Key Code TRU
Applicable Documents
Module Configuration Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configuration
Figure 1. TRU functional block diagram
Figure 1. TRU functional block diagram (cont)
Figure 2. TRU pin assignment
Alternate Test Methods
Figure 3. TRU operating temperature and life test circuit
Figure 4. Operating temperature and life test waveforms
Input Pulse Parameters for Item J01
Figure 5. TRU component temperature test circuit
Figure 6. TRU vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Input Parameters (cont)
Input Parameters (cont)
Output Parameters
Output Parameters (cont)
Output Parameters (cont)
Dynamic Parameters
PROM Contents by HEX address
Functional Description of I/O pins
Functional Description of I/O pins (cont)
Functional Description of I/O pins (cont)
Functional Description of I/O pins (cont)
Description of Tests
Description of Tests (cont)
Functional Test Vectors
Table II. Isolation Test
Table II. Isolation Test (cont)
Table II. Isolation Test (cont)
Table III. Continuity test
Table IV. Power supply stress test
Table V. Input breakdown current test
Table V. Input breakdown current test (Cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Table VI. Input clamp diode voltage test
Table VI. Input clamp diode voltage test (cont)
Input clamp diode voltage test tolerance table
Procedure required to perform the test
Table VII. Output short circuit current test
Table VII. Output short circuit current test (cont)
Output short circuit current test tolerance table
Procedure required to perform the test
Table VIII. Input current, high level, test
Table VIII. Input current, high level, test (cont)
Input current, high level, test tolerance table
Procedure required to perform the test
Table IX. Input current, low level, test
Table IX. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Table X. Output voltage, high level, test
Table X. Output voltage, high level, test (cont)
Output voltage, high level, test tolerance table
Procedure required to perform the test
Figure 7. Logic laod circuit
Value of R2 foe each output load
Table XI. Output voltage, low level, test
Table XI. Output voltage, low level, test (cont)
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table XII. Output leakage current, high level, test
Output leakage current, high level, test tolerance table
Procedure required to perform the test
Table XIII. Output lekage current, low level, test
Output lekage current, low level, test tolerance table
Procedure required to perform the test
Table XIV. Power supply current test
Table XV. Functional Test
Procedure required to perform the test
Figure 8. Input timing parameters for table XV
Input parameters
Table XVI. Dynamic test
Procedure required to perform the test
Table XVI. Dynamic test (cont)
Figure 9. Sample input waveforms for table XVI
Table XVII. Dynamic parameters
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Figure 10a. Dynamic waveforms for table XVII
Figure 10b. Dynamic waveforms for table XVII
Figure 10c. Dynamic waveforms for table XVII
Figure 10d. Dynamic waveforms for table XVII
Figure 10e. Dynamic waveforms for table XVII
Figure 10f. Dynamic waveforms for table XVII
Table XVIII. Power supply filter capacitance test
Table XIX. Power supply transient amplitude test
Table XIX. Power supply transient amplitude test (cont)
Figure 11. Power supply transient amplitude waveform for table XIX
Table XX. Output crosstalk, high level, test
Table XX. Output crosstalk, high level, test (cont)
Output crosstalk, high level, test tolerance table
Procedure required to perform the test
Table XXI. Output crosstalk, low level, test
Table XXI. Output crosstalk, low level, test (cont)
Output crosstalk, low level, test tolerance table
Procedure required to perform the test
Figure 12. Output crosstalk, high and low level, test waveforms for tables XX and XXI
Figure 13. Output crosstalk, high and low level, test circuit for tables XX and XXI
Table XXII. Output crosstalk duration test
Table XXII. Output crosstalk duration test (cont)
Output crosstalk duration test tolerance table
Procedure required to perform the test
Figure 14.output crosstalk duration test waveform for table XXII
Table XXIII. Input capacitance test
Table XXIII. Input capacitance test (cont)
Table XXIII. Input capacitance test (cont)
Table XXIII. Input capacitance test (cont)
Table XXIV. Output capacitance test
Output capacitance test tolerance table
Table XXV. Threshold test
Input threshold levels
Table XXVI. Disable time test
Table XXVI. Disable time test (cont)
Table XXVI. Disable time test (cont)
Table XXVI. Disable time test (cont)
Table XXVI. Disable time test (cont)
Table XXVI. Disable time test (cont)
Table XXVI. Disable time test (cont)
Table XXVI. Disable time test (cont)
Disable time test tolerance table
Figure 15. Disable time test circuit for test conditions Z1-Z48
Figure 16. Disable time test waveforms for test conditions Z1-Z48
Figure 16. Disable time test waveforms for test conditions Z1-Z48 (cont)
Figure 17. Disable time test circuit for test conditions Z49-Z56
Figure 18. Disable time test waveforms for test conditions Z48-Z56
Figure 18. Disable time test waveforms for test conditions Z48-Z56 (cont)
Table XXVII. Output pulse width and pulse period test
Output pulse width and pulse period test tolerance table
Table XXVII. Output pulse width and pulse period test (cont)
Figure 19. Output pulse width and pulse period test waveforms for table XXVII
Standardization Document Improvement Proposal

Modules, Digital, Standard Electronic, Clock, Microprocessor Module, Key Code TRU

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