Modules, Standard Electronic, MIL-STD-1553 Dumb RTU Module, Key Code UKT

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Modules, Standard Electronic, MIL-STD-1553 Dumb RTU Module, Key Code UKT

Modules, Standard Electronic, MIL-STD-1553 Dumb RTU Module, Key Code UKT
Applicable Documents
General Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Quality Assurance Provisions
Figure 1. UKT functional block diagram
Figure 1. UKT functional block diagram (cont)
Figure 1. UKT functional block diagram (cont)
Figure 2. UKT pin assignment
Alternate Test Methods
Figure 3.UKT operating temperature, component temperature and life test circuit
Figure 3.UKT operating temperature, component temperature and life test circuit (cont)
Figure 4. UKT vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Input Parameters (cont)
Output Parameters
Output Parameters (cont)
Class I and II dynamic parameters
Class I and II dynamic parameters (cont)
Class I and II dynamic parameters (cont)
Class I and II dynamic parameters (cont)
Class I and II dynamic parameters (cont)
Class I and II dynamic parameters (cont)
Class I and II dynamic parameters (cont)
Class I and II dynamic parameters (cont)
Class I and II dynamic parameters (cont)
Class I and II dynamic parameters (cont)
Module Function
Figure 5a. UKT timing waveforms
Figure 5b. UKT timing waveforms
Figure 5c. UKT timing waveforms
Figure 5d. UKT timing waveforms
Figure 5e. UKT timing waveforms
Figure 6. UKT receive sequence timing waveforms
Figure 6. UKT receive sequence timing waveforms (cont)
Figure 6. UKT receive sequence timing waveforms (cont)
Figure 7. UKT transmit sequence timing waveforms
Figure 7. UKT transmit sequence timing waveforms (cont)
Figure 7. UKT transmit sequence timing waveforms (cont)
Figure 8a. UKT timing waveforms for driving data bus (assumed channel is selected)
Figure 8b. UKT timing waveforms for latching dat from data bus
Figure 9. Dual redundant RTU block diagram
Figure 9. Dual redundant RTU block diagram (cont)
Figure 9. Dual redundant RTU block diagram (cont)
Figure 10. MIL-STD-1553B bus controller block diagram
Figure 10. MIL-STD-1553B bus controller block diagram (cont)
Figure 10. MIL-STD-1553B bus controller block diagram (cont)
Figure 11. Dual redundant bus controller block diagram
Figure 11. Dual redundant bus controller block diagram (cont)
Figure 11. Dual redundant bus controller block diagram (cont)
Figure 11. Dual redundant bus controller block diagram (cont)
Functional Description I/O Pins
Functional Description I/O Pins (cont)
Functional Description I/O Pins (cont)
Functional Description I/O Pins (cont)
Functional Description I/O Pins (cont)
Functional Description I/O Pins (cont)
Functional Description I/O Pins (cont)
Functional Description I/O Pins (cont)
Functional Description I/O Pins (cont)
Functional Description I/O Pins (cont)
Functional Test Vectors
Module Handling Considerations
Table II. Isolation test
Table II. Isolation test (Cont)
Table II. Isolation test (Cont)
Table III. Continuity test
Table III. Continuity test (cont)
Table IV. Power supply stress test
Table IV. Power supply stress test (cont)
Table V. Transformer short circuit stress test
Figure 12. Transformer short circuit stress test circuit for table V
Figure 13. Test circuit waveforms for figure 12
Table VI. Input breakdown current test
Table VI. Input breakdown current test (cont)
Table VI. Input breakdown current test (cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Table VII. Output short circuit current test
Output short circuit current test tolerance table
Procedure required to perform the test
Table VIII. Input current, high level, test
Table VIII. Input current, high level, test (cont)
Input current, high level, test tolerance table
Procedure required to perform the test
Table IX. Input current, low level, test
Table IX. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Table X. Input clamp diode voltage test
Input clamp diode voltage test tolerance table
Procedure required to perform the test
Table XI. Output voltage, high level, test
Table XI. Output voltage, high level, test (cont)
Output voltage, high level, test tolerance table
Procedure required to perform the test
Figure 14. Logic load circuit
Value of R2 for each output load
Table XII. Output voltage, low level, test
Table XII. Output voltage, low level, test (cont)
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table XIII. Output lekage current, high level, test
Output lekage current, high level, test tolerance table
Procedure required to perform the test
Table XIV. Output lekage current, low level, test
Output lekage current, low level, test tolerance table
Procedure required to perform the test
Table XV. Power supply current test
Procedure required to perform the test
Table XVI. Functional test
Procedure required to perform the test
Inpur Pins Pattern Voltage
Table XVII. Dynamic test
Procedure required to perform the test
Input Waveforms Characteristics
Figure 16. Transformer I/O voltages for table XVII
Figure 17. Transformer load circuit
Table XVIII. Power supply filter capacitance test
Table XIX. Input capacitance test
Table XIX. Input capacitance test (cont)
Input capacitance test tolerance table
Table XX. Output capacitance test
Output capacitance test tolerance table
Table XXI. Power supply transient amplitude test
Procedure required to perform the test
Figure 18. Power supply transient amplitude waveform for table XXI
Table XXII. Transformer impedance test
Figure 19. Transformer impedance test circuit for table XXII
Table XXIII. Receiver common mode test
Table XXIII. Receiver common mode test (cont)
Figure 20. Receiver common mode test circuit for table XXIII
Figure 21. Receiver common mode test circuit waveforms for table XXIII
Table XXIV. Transient functional test
Table XXIV. Transient functional test (cont)
Table XXIV. Transient functional test (cont)
Figure 22. Transient functional test circuit for table XXIV
Figure 23. Transient functional test circuit waveforms for table XXIV
Table XXV. Receiver no response test
Figure 24. Receiver no response test circuit for table XXV
Figure 25. Receiver no response test circuit waveforms for table XXV
Table XXVI. Output symmetry test
Table XXVI. Output symmetry test (cont)
Figure 26. Output symmetry test circuit for table XXVI
Figure 27. Output symmetry test circuit waveform for table XXVI
Table XXVII. Output crosstalk, high level, test
Table XXVII. Output crosstalk, high level, test (cont)
Table XXVII. Output crosstalk, high level, test (cont)
Table XXVII. Output crosstalk, high level, test (cont)
Output crosstalk, high level, test tolerance table
Procedure required to perform the test
Figurer 28. Output crosstalk test ciruit waveforms, high and low level, for tables XXVII and XXVIII
Figure 29. Output crosstalk, high and low level, test circuit for tables XXVII and XXVIII
Table XXIX. Receiver functional test
Table XXIX. Receiver functional test (cont)
Table XXIX. Receiver functional test (cont)
Table XXIX. Receiver functional test (cont)
Figure 30. Receiver functional test circuit for table XXIX
Figure 31. Receiver functional test circuit waveforms for table XXIX

Modules, Standard Electronic, MIL-STD-1553 Dumb RTU Module, Key Code UKT

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