Modules, Digital, Standard Electronic, 68000 Control/Maintenance Module, Key Code ADP

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Modules, Digital, Standard Electronic, 68000 Control/Maintenance Module, Key Code ADP

Modules, Digital, Standard Electronic, 68000 Control/Maintenance Module, Key Code ADP
Applicable Documents
Module Configuration Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configuration
Figure 1. ADP functional block diagram
Figure 1. ADP functional block diagram (cont)
Figure 1. ADP functional block diagram (cont)
Figure 2. ADP pin assignment
Figure 1. ADP functional block diagram (cont)
Figure 2. ADP pin assignment
Alternate Test Methods
Figure 3. ADP operating temperature and life test circuit
Figure 4. Operating temperature and life test waveforms
Input pulse parameters for item J01-2
Figure 5. ADP component temperature test circuit
Figure 6. Component temperature test waveforms
Input pulse parameters for item J01
Figure 7. ADP vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Output Parameters
Output Parameters (cont)
Output Parameters (cont)
Dynamic Parameters
Description of I/O Pins
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of Tests
Functional Test Vectors
Table II. Isolation test
Table III. Continuity test
Table IV. Power supply stress test
Table V. Input breakdown current test
Table V. Input breakdown current test (cont)
Table V. Input breakdown current test (cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Table VI. Input clamp diode voltage test
Table VI. Input clamp diode voltage test (cont)
Table VI. Input clamp diode voltage test (cont)
Input clamp diode voltage test tolerance table
Procedure required to perform the test
Table VII. Output short circuit current test
Table VII. Output short circuit current test (cont)
Output short circuit current test tolerance table
Procedure required to perform the test
Table VIII. Input current, highlevel, test
Table VIII. Input current, highlevel, test (cont)
Table VIII. Input current, highlevel, test (cont)
Input current, highlevel, test tolerance table
Procedure required to perform the test
Table IX. Input current, low level, test
Table IX. Input current, low level, test (cont)
Table IX. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Table X. Output voltage, high level, test
Table X. Output voltage, high level, test (cont)
Output voltage, high level, test tolerance table
Procedure required to perform the test
Figure 8. Logic load circuit
Value of R2 for each output load
Table XI. Output voltage, low level, test
Table XI. Output voltage, low level, test (cont)
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table XII. Output leakage current, high level, test
Procedure required to perform the test
Table XIII. Output leakage current, low level, test
Procedure required to perform the test
Table XIV. Power supply current test
Table XV. Functional test
Procedure required to perform the test
Figure 9. Input timing parameters for table XV
Figure 9. Input timing parameters for table XV (cont)
Input Parameters for Figure 9
Table XVI. Dynamic test
Procedure required to perform the test
Figure 10. Sample input waveform for table XVI
Table XVII. Dynamic parameters
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Figure 11a. Dynamic waveforms for table XVII
Figure 11b. Dynamic waveforms for table XVII
Figure 11c. Dynamic waveforms for table XVII
Figure 11d. Dynamic waveforms for table XVII
Figure 11e. Dynamic waveforms for table XVII
Figure 11f. Dynamic waveforms for table XVII
Figure 11g. Dynamic waveforms for table XVII
Figure 11h. Dynamic waveforms for table XVII
Figure 11i. Dynamic waveforms for table XVII
Table XVIII. Power supply filter capacitance test
Table XIX. Power supply transient amplitude test
Procedures required to perform the test
Figure 12. Power supply transient amplitude waveform for table XIX
Table XX. Output crosstalk, high level, test
Table XX. Output crosstalk, high level, test (cont)
Output crosstalk, high level, test tolerance table
Procedure required to perform the test
Table XXI. Output crosstalk, low level, test
Table XXI. Output crosstalk, low level, test (cont)
Output crosstalk, low level, test tolerance table
Procedure required to perform the test
Figure 13. Output crosstalk, high and low level, test waveforms for tables XX and XXI
Figure 14. Output crosstalk, high and low level, test circuit for tables XX and XXI
Table XXII. Output crosstalk duration, low level, test
Output crosstalk duration, low level, test tolerance table
Figure 15. Output crosstalk duration waveforms for table XXII
Table XXIII. Input capacitance test
Table XXIII. Input capacitance test (cont)
Table XXIII. Input capacitance test (cont)
Input capacitance test tolerance table
Table XXIII. Input capacitance test (Notes)
Table XXIV. Output capacitance test
Table XXIV. Output capacitance test (Notes)
Table XXV. Disable time test
Table XXV. Disable time test (Cont)
Figure 16. Disable time test circuit for table XXV
Figure 17. Disable time test waveforms for table XXV
Figure 17. Disable time test waveforms for table XXV (Notes)
Table XXVI. Threshold test
Table XXVI. Threshold test (Notes)

Modules, Digital, Standard Electronic, 68000 Control/Maintenance Module, Key Code ADP

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