Modules, Standard Electronic, Converter, Analog/Digital, Key Code CKA

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Modules, Standard Electronic, Converter, Analog/Digital, Key Code CKA

Modules, Standard Electronic, Converter, Analog/Digital, Key Code CKA
Applicable Documents
Module Configuration Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Quality Assurance Provisions
Figure 1. CKA functional block diagram and pin assignments
Alternate Test Methods
Figure 2. Operating temperature, component temperatrue and life test circuit
Figure 2. Operating temperature, component temperatrue and life test circuit - Notes
Figure 3. Vibration test circuit
Thermal Shock Test
Module Descriptions
Module Descriptions (cont)
Analog-to-Digital Converter
Sample and Hold
Functional Description of I/O Pins
Functional Description of I/O Pins (cont)
Description of Tests
Description of Tests (cont)
Table II. Isolation test
Table II. Isolation test (cont)
Figure 4. Isolation test circuit for table II
Table III. Continuity test
Table III. Continuity test (cont)
Figure 5. Continuity test circuit for table III
Table IV. Power supply stress test
Figure 6. Power supply stress test circuit for table IV
Table V. Breakdown current test
Table VI. Short circuit current test
Figure 7. Short circuit current test circuit for table VI
Table VII. Power supply current test
Figure 8. Power supply current test circuit for table VII
Figure 9. Timing diagrams
Table VIII. Filter and input capacitance test
Figure 10. Filter and input capacitance test circuit for table VIII
Table IX. Filter inductance test
Figure 11. Power supply filter inductance test circuit for table IX
Table X. 10 V divider test
Figure 12. 10 V divider test circuit for table X
Table XI. Input current, high level, test
Table XII. Input current, low level, test
Figure 13. Breakdown and input current, high and low level, test circuit for tables V, XI and XII
Table XIII. Output voltage, high level, test
Table XIV. Output voltage, low level, test
Figure 14. Output voltage, high and low level, test circuit for tables XIII and XIV
Figure 15. Logic load circuit
Figure 16. STS logic load "1" voltage test circuit
Table XV. Leakage current test
Table XV. Leakage current test (cont)
Figure 17. Leakage current test circuit for table XV
Table XVI. Reference voltage test
Figure 18. Reference voltage test circuit for table XVI
Table XVII. Conversion time test
Figure 19. Conversion time test circuit for table XVII
Table XVIII. Operating modes test
Table XVIII. Operating modes test (cont)
Figure 20. Operating modes test circuit for table XVIII
Table XIX. Supply sensitivity test
Figure 21. Test circuit for tables XIX, XX, XXI, XXII, XXIII and XXV
Figure 22. Transition uncertainty
Table XX. Missing code check test
Figure 23. Missing code check test algorithm for table XX
Table XXI. ADC offset voltage test
Table XXII. ADC gain error test
Table XXIII. ADC linearity error test
Table XXIII. ADC linearity error test (cont)
Table XXIII. ADC linearity error test (cont)
Figure 24. Linearity error test algorithm for tables XXI, XXII and XXIII
Figure 25. Endpoint staightline method for integral linearity
Table XXIV. ADC transition time test
Table XXIV. ADC transition time test (cont)
Figure 26. Transition time test circuit for table XXIV
Figure 27a. Transition time test waveforms
Figure 27b. Transition time test waveforms
Table XXV. ADC transition error test
Figure 28. ADC transition error test algorithm for table XXV
Table XXVI. S/H input impedance test
Figure 29. S/H input impedance test circuit for table XXVI
Table XXVII. S/H acquisition limit test
Figure 30. S/H acquisition time test circuit for table XXVII
Figure 31. S/H acquisition time test waveforms for table XXVII
Table XXVIII. S/H droop rate test
Figure 32. S/H droop rate test circuit for table XXVIII
Figure 33. S/H droop rate test waveforms for table XXVIII
Table XXIX. I/A offset voltage test
Figure 34. I/A offset voltage test circuit for table XXIX
Table XXX. I/A input bias and offset current test
Figure 35. I/A input bias and offset current test circuit for table XXX
Table XXXI. I/A power supply sensitivity test
Figure 36. I/A power supply sensitivity test circuit for table XXXI
Table XXXII. I/A common mode rejection ratio test
Figur e37. I/A common mode rejection ratio test circuit for table XXXII
Table XXXIII. I/A output swing test
Figure 38. I/A output swing test circuit for table XXXIII
Table XXXIV. I/A settling time test
Figure 39. I/A settling time test circuit for table XXXIV
Figure 40. I/A settling time waveforms for table XXXIV
Table XXXV. I/A input resistance test
Figure 41. I/A input resistance test circuit for table XXXV
Table XXXVI. I/A gain accuracy test
Figure 42. I/A gain accuracy test circuit for table XXXVI
Table XXXVII. I/A slew rate test
Figure 43. I/A slew rate test circuit for table XXXVII
Figure 44. I/A slew rate waveforms for table XXXVII
Standardization Document Improvement Proposal

Modules, Standard Electronic, Converter, Analog/Digital, Key Code CKA

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