Modules, Digital, Ultraviolet Light Erasable Programmable Read Only Memory (UV EPROM) Module

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Modules, Digital, Ultraviolet Light Erasable Programmable Read Only Memory (UV EPROM) Module

Modules, Digital, Ultraviolet Light Erasable Programmable Read Only Memory (UV EPROM) Module
Applicable Documents
Application Requirements
Key Code
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configurations
Test Equipment
Figure 1. Functional block diagram
Figure 2. Pin assignment
Alternate Test Methods
Figure 3a. Operating temperature and life test circuit
Figure 3b. RAM address counter circuit
Figure 4. Operating temperature and life test waveforms
Figure 5. Component temperature test circuit
Figure 6. Vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Output Parameters
Standby Mode
Description of I/O Pins
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of Tests
Functional Test Vectors
Table II. Isolation test
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Isolation test tolerance table
Table II. Isolation test (cont)
Table III. Continuity test
Table IV. Input breakdown current test
Table IV. Input breakdown current test (cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Table V. Output short circuit current test
Procedure required to perform the test
Table V. Output short circuit current test (cont)
Table VI. Power supply stress test
Table VII. Input clamp diode voltage test
Table VII. Input clamp diode voltage test (cont)
Procedure required to perform the test
Table VIII. Input current, low level, test
Table VIII. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Procedure required to perform the test (cont)
Table IX. Input current, high level, test
Table IX. Input current, high level, test (cont)
Input current, high level, test tolerance table
Procedure required to perform the test
Table X. Output laekage current, high level, test
Output laekage current, high level, test tolerance table
Procedure required to perform the test
Table XI. Output laekage current, low level, test
Output laekage current, low level, test tolerance table
Procedure required to perform the test
Table XII. Output voltage, high level, test
Output voltage, high level, test tolerance table
Procedure required to perform the test
Figure 7. Logic load circuit
Table XIII. Output voltage, low level, test
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table XIV. Power supply current test
Procedure required to perform the test
Table XV. Functional test
Memory test pattern for UV EPROMs
Table XVI. Dynamic test
Procedure required to perform the test
Table XVI. Dynamic test (cont)
Table XVII. Dynamic parameters
Figure 8. Dynamic waveforms for table XVII
Table XVIII. Enable/Disable time test
Table XVIII. Enable/Disable time test (cont)
Table XVIII. Enable/Disable time test (cont)
Table XVIII. Enable/Disable time test (cont)
Enable/Disable time test tolerance table
Figure 9. Enable/Disable time test waveforms for table XVIII
Table XIX. Capacitance test
Table XIX. Capacitance test (cont)
Table XIX. Capacitance test (cont)
Capacitance test tolerance table
Table XX. Output crosstalk test
Table XX. Output crosstalk test (cont)
Table XX. Output crosstalk test (cont)
Output crosstalk test tolerance table
Table XX. Output crosstalk test (cont)
Figure 10. Output crosstalk, high and low level, test circuit for table XX
Figure 11. Output crosstalk, high and low level, test waveforms for table XX
Table XXI. Power supply transient amplitude test
Figure 12. Power supply transient amplitude test circuit for table XXI
Figure 13. Power supply transient amplitude waveform for table XXI
Table XXII. Power supply filter capacitance test
Table XXIII. Propagation delay time test
Propagation delay time test tolerance table
Procedure required do perform the test
Figure 14. Propagation delay test waveforms for table XXIII
Table XXIV. Erasing test
Table XXV. Programming test
Table XXV. Programming test (cont)
Table XXVI. Margin test
Table XXVI. Margin test (cont)
Figure 15. Module read waveforms for table XXVI
Figure 15. Module read waveforms for table XXVI (cont)
Appendix. Module Programming
Fast Programming Algorithm
Figure 1a. Programming algorithm for UV EPROM
Figure 1b. Programming algorithm for UV EPROM
Figure 2. Programming timing characteristics for UV EPROM
Table I. Programming timing characteristics for UV EPROM
Stabdardization Document Improvement Proposal

Modules, Digital, Ultraviolet Light Erasable Programmable Read Only Memory (UV EPROM) Module

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