Modules, Standard Electronic, MIL-STD-1397 Parallel Channel Control Module, Key Code AWB

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Modules, Standard Electronic, MIL-STD-1397 Parallel Channel Control Module, Key Code AWB

Modules, Standard Electronic, MIL-STD-1397 Parallel Channel Control Module, Key Code AWB
Applicable Documents
General Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Quality Assurance Provisions
Figure 1. AWB functional block diagram
Figure 1. AWB functional block diagram (cont)
Figure 2. AWB pin assignment
Alternate Test Methods
Figure 3. AWB operating temperature and component temperature test circuit
Figure 4. AWB vibration test circuit
Thermal Shock Test
Figure 5. AWB life test circuit
Module Description
Input Parameters
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Output Parameters
Output Parameters (cont)
Output Parameters (cont)
Output Parameters (cont)
Output Parameters (cont)
Class I and II Dynamic Parameters
Class I and II Dynamic Parameters (cont)
Class I and II Dynamic Parameters (cont)
Module Function
IOC Data Bus Latches
Description of I/O Pins
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Functional Test Vectors
Table II. Isolation test
Isolation test tolerance table
Table II. Isolation test (cont)
Figure 6. Isolation test circuit for table II
Table III. Continuity test
Figure 7. Continuity test circuit for table III
Table IV. Power supply stress test
Figure 8. Vcc stress test circuit for table IV
Table V. Input breakdown current test
Input breakdown current test tolerance table
Procedure required to perform the test
Table VI. Output shorct circuit current test
Table VI. Output shorct circuit current test (cont)
Table VI. Output shorct circuit current test (cont)
Output shorct circuit current test tolerance table
Procedure required to perform the test
Table VII. Input current, high level, test
Table VII. Input current, high level, test (cont)
Table VII. Input current, high level, test (cont)
Input current, high level, test tolerance table
Procedure required to perform the test
Table VIII. Input current, low level, test
Table VIII. Input current, low level, test (cont)
Table VIII. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Table IX. Output voltage, high level, test
Table IX. Output voltage, high level, test (cont)
Table IX. Output voltage, high level, test (cont)
Output voltage, high level, test tolerance table
Procedure required to perform the test
Figure 9. Logic load circuit
Value of R2 for each output load
Table X. Output voltage, low level, test
Table X. Output voltage, low level, test (Cont)
Table X. Output voltage, low level, test (Cont)
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table XI. Output leakage current, high level, test
Procedure required to perform the test
Table XII. Input clamp diode voltage test
Table XII. Input clamp diode voltage test tolerance table
Table XIII. Power supply filter capacitance test
Figure 10. Power supply filter capacitance test circuit for table XIII
Table XIV. Power supply current test
Table XV. Functional test
Procedure required to perform the test
Figure 11. Input timing parameters for table XV
Table XVI. Dynamic test
Table XVI. Dynamic test (cont)
Table XVI. Dynamic test (cont)
Table XVII. Dynamic parameters
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Figure 12a. Dynamic waveforms for table XVII
Figure 12b. Dynamic waveforms for table XVII
Table XVIII. Input and output capacitance test
Table XVIII. Input and output capacitance test (cont)
Table XVIII. Input and output capacitance test (cont)
Input and output capacitance test tolerance table
Table XVIII. Input and output capacitance test (cont)
Figure 13. Input and output capacitance test circuit for table XVIII
Table XIX. Power supply transient amplitude test
Procedure required to perfom the test
Figure 14. Power supply transient amplitude waveform for table XIX
Figure 15. Power supply transient amplitude test circuit for table XIX
Address
Standardization Document Improvement Proposal

Modules, Standard Electronic, MIL-STD-1397 Parallel Channel Control Module, Key Code AWB

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