Modules, Standard Electronic, IOC Data Bus Lower Module, Key Code AWG

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Modules, Standard Electronic, IOC Data Bus Lower Module, Key Code AWG

Modules, Standard Electronic, IOC Data Bus Lower Module, Key Code AWG
Applicable Documents
Module Configuration Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configuration
Figure 1. AWG functional block diagram
Figure 1. AWG functional block diagram (cont)
Figure 2. AWG pin assignment
Quality Assurance Provisions
Component Temperature Test
Figure 3. AWG operating temperature and component temperature test circuit
Figure 4. AWG vibration test circuit
Figure 5. AWG life test circuit
Module Description
Input Parameters
Input Parameters (Cont)
Input Parameters (Cont)
Input Parameters (Cont)
Output Parameters
Output Parameters (cont)
Output Parameters (cont)
Output Parameters (cont)
Class I and II Dynamic Parameters
Class I and II Dynamic Parameters (cont)
Class I and II Dynamic Parameters (cont)
Class I and II Dynamic Parameters (cont)
Class I and II Dynamic Parameters (cont)
Module Function
Transmit Register
Memory Data Register
Description of I/O Pins
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Functional Test Vectors
Table II. Isolation test
Table II. Isolation test (cont)
Figure 6. Isolation test circuit for table II
Table III. Continuity test
Figure 7. Continuity test circuit for table III
Table IV. Power supply stress test
Figure 8. Vcc stress testcircuit for table IV
Table V. Input breakdown current test
Table V. Input breakdown current test (Cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Table VI. Output short circuit current test
Table VI. Output short circuit current test (cont)
Table VI. Output short circuit current test (cont)
Procedure required to perform the test
Procedure required to perform the test (cont)
Table VII. Input current, high level, test
Table VII. Input current, high level, test (cont)
Table VII. Input current, high level, test (cont)
Input current, high level, test tolerance table
Procedure required to perform the test
Table VIII. Input current, low level, test
Table VIII. Input current, low level, test (cont)
Table VIII. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Table IX. Output voltage, high level, test
Table IX. Output voltage, high level, test (cont)
Output voltage, high level, test tolerance table
Procedure required to perform the test
Figure 9. Logic load circuit
Value of R2 for each output load
Table X. Output voltage, low level, test
Table X. Output voltage, low level, test (cont)
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table XI. Input clamp diode voltage test
Table XI. Input clamp diode voltage test (cont)
Procedure required to perform the test
Table XII. Power supply filter capacitance test
Figure 10. Power supply filter capacitance test circuit for table XII
Table XIII. Power supply current test
Table XIV. Functional test
Procedure required to perform the test
Figure 11. Input timing parameters for table XIV
Figure 11. Input timing parameters for table XIV (cont)
Table XV. Dynamic test
Table XV. Dynamic test (cont)
Table XV. Dynamic test (cont)
Table XVI. Dynamic parameters
Table XVI. Dynamic parameters (Cont)
Table XVI. Dynamic parameters (Cont)
Table XVI. Dynamic parameters (Cont)
Table XVI. Dynamic parameters (Cont)
Figure 12a. Dynamic waveforms for table XVI
Figure 12b. Dynamic waveforms for table XVI
Figure 12c. Dynamic waveforms for table XVI
Figure 12d. Dynamic waveforms for table XVI
Figure 12e. Dynamic waveforms for table XVI
Table XVII. Input and output capacitance test
Table XVII. Input and output capacitance test (cont)
Table XVII. Input and output capacitance test (cont)
Input and output capacitance test tolerance table
Input and output capacitance test tolerance table (cont)
Figure 13. Input and output capacitance test circuit for table XVII
Table XVIII. Input clamp diode latch up test
Table XVIII. Input clamp diode latch up test (Cont)
Table XIX. Power supply transient amplitude test
Table XIX. Power supply transient amplitude test (Cont)
Figure 14. Power supply transient amplitude waveforms for table XIX
Figure 15. Power supply transient amplitude test circuit for table XIX
Address
Standardization Document Improvement Proposal

Modules, Standard Electronic, IOC Data Bus Lower Module, Key Code AWG

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