Modules, Standard Electronic Direct Memory Interface I Module, Key Code DWG

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Modules, Standard Electronic Direct Memory Interface I Module, Key Code DWG

Modules, Standard Electronic Direct Memory Interface I Module, Key Code DWG
Specification and standards
Module configuration requirements
Table 1. Module electrical requirements
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
End-of-life limits
Figure 1. DWG functional block diagram
Figure 2. DWG pin assignment
Multiple testing of pins
Figure 3. DWG operating temperature and component temperature test circuit
Figure 4. DWG vibration test circuit
Thermal shock test
Figure 5. DWG life test circuit
Module description
Input parameters
Input parameters-cont.
Input parameters-cont.
Output parameters
Class I dynamic parameters
Class I dynamic parameters-cont.
DMA read operations
DMA read/modify/write operations
Description of I/O pins
Description of I/O pins-cont.
Description of I/O pins-cont.
Functional test vectors
Table 2. Isolation test
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Table 2. Isolation test-cont.
Isolation test tolerance table
Figure 6. Isolation test circuit for table 2
Table 3. Continuity test
Figure 7. Continuity test circuit for table 3
Table 4. Power supply stress test
Figure 8. Vcc stress test circuit for table 4
Table 5. Input breakdown current test
Input breakdown current test tolerance table
Notes-cont.
Table 6. Output short circuit current test
Output short circuit current test tolerance table
Notes-cont.
Table 7. Input current, high level, test
Table 7. Input current, high level, test-cont.
Input current, high level, test tolerance table
Notes-cont.
Tale 3. Input current, low level, test
Tale 3. Input current, low level, test-cont.
Input current, low level, test tolerance table
Notes-cont.
Table 9. Output voltage, high level, test
Output voltage, high level, test tolerance table
Notes-cont.
Figure 9. Logic load circuit
Notes-cont.
Table 10. Output voltage, low level, test
Output voltage, low level, test tolerance table
Notes-cont.
Table 11. Input clamp diode voltage test
Input clamp diode voltage test tolerance table
Table 12. Power supply filter capacitance test
Figure 10. Power supply filter capacitance test circuit for table 12
Table 13. Power supply current test
Notes-cont.
Table 14. Functional test
Notes-cont.
Table 15. Dynamic test
Dynamic test tolerance table
Notes-cont.
Table 16. Dynamic parameters
Table 16. Dynamic parameters-cont.
Figure 11. Dynamic waveforms for table 16
Table 17. Input and output capacitance test
Table 17. Input and output capacitance test-cont.
Input and output capacitance test tolerance table
Figure 12. Input and output capacitance test circuit for table 17
Table 18. Input clamp diode latchup test
Notes-cont.
Table 19. Power supply transient amplitude test
Notes-cont.
Figure 13. Powr supply transient amplitude waveform for table 19
Figure 14. Power supply transient amplitude test circuit for table 20
Standardization Document Improvement Proposal

Modules, Standard Electronic Direct Memory Interface I Module, Key Code DWG

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