Modules, Standard Electronic High Performance Address Generation Module, Key Code CWK

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Modules, Standard Electronic High Performance Address Generation Module, Key Code CWK

Modules, Standard Electronic High Performance Address Generation Module, Key Code CWK
Specifications and standards
Failure rate requirements
Table 1. Module electrical requirements
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Quality Assurance Provisions
Figure 1. CWK functional block diagram
Figure 1. CWK functional block diagram-cont.
Figure 2. CWK pin assignment
Qualification testing
Life test
Figure 3. CWK operating temperature and component temperature test circuit
Figure 4. CWK vibration test circuit
Figure 5. CWK life test circuit
Module description
Input parameters
Input parameters-cont.
Input parameters-cont.
Input parameters-cont.
Output parameters
Output parameters-cont.
Output parameters-cont.
Output parameters-cont.
Output parameters-cont.
Class I and II dynamic parameters
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Memory address register
Memory address register extension
Page data selector
Nondestructive Readout (NDRO) detector
Microcontrol/destinaton decoder
Description of I/O pins-cont.
Description of I/O pins-cont.
Description of I/O pins-cont.
Description of I/O pins-cont.
Functional test vectors
Table 2. Isolation test
Notes-cont.
Figure 6. Isolation test circuit for table 2
Table 3. Continuity test
Figure 7. Continuity test circuit for table 3
Table 4. Power supply stress test
Figure 8. Vcc stress test circuit for table 4
Table 5. Input breakdown current test
Input breakdown current test tolerance table
Input breakdown current test tolerance table-cont.
Table 6. Output short circuit current test
Table 6. Output short circuit current test-cont.
Table 6. Output short circuit current test-cont.
Table 6. Output short circuit current test-cont.
Table 6. Output short circuit current test-cont.
Output short circuit current test tolerance table
Output short circuit current test tolerance table-cont.
Notes-cont.
Table 7. Input current, high level, test
Table 7. Input current, high level, test-cont.
Input current, high level, test tolerance table
Input current, high level, test tolerance table-cont.
Notes-cont.
Table 8. Input current, low level, test
Table 8. Input current, low level, test-cont.
Input current, low level, test tolerance table
Input current, low level, test tolerance table-cont.
Notes-cont.
Table 9. Output voltage, high level, test
Table 9. Output voltage, high level, test-cont.
Table 9. Output voltage, high level, test-cont.
Table 9. Output voltage, high level, test-cont.
Table 9. Output voltage, high level, test-cont.
Output voltage, high level, test tolerance table
Notes
Figure 9. Logic load circuit
Notes-cont.
Table 10. Output voltage, low level, test
Table 10. Output voltage, low level, test-cont.
Table 10. Output voltage, low level, test-cont.
Table 10. Output voltage, low level, test-cont.
Table 10. Output voltage, low level, test-cont.
Output voltage, low level, test tolerance table
Notes-cont.
Table 11. Output leakage current, high and low level, test
Table 11. Output leakage current, high and low level, test-cont.
Output leakage current, high and low level, test tolerance table
Notes-cont.
Table 12. Input clamp diode voltage test
Input clamp diode voltage test tolerance table
Input clamp diode voltage test tolerance table-cont.
Table 13. Powe supply filter capacitance test
Figure 10. Power supply filter capacitance test circuit for table 13
Table 14. Powe supply current test
Table 15. Functional test
Notes-cont.
Figure 11. Input timing parameters for table 15
Notes-cont.
Table 16. Dynamic test
Dynamic test tolerance table-cont.
Notes-cont.
Table 17. Dynamic parameters
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Figure 12a. Dynamic waveforms for table 17
Figure 12b. Dynamic waveforms for table 17
Figure 12c. Dynamic waveforms for table 17
Table 18. Input and output capacitance test
Table 18. Input and output capacitance test-cont.
Table 18. Input and output capacitance test-cont.
Input and output capacitance test tolerance table
Input and output capacitance test tolerance table-cont.
Figure 13. Input and output capacitance test circuit for table 18
Table 19. Power supply transient amplitude test
Notes-cont.
Figure 14. Power supply transient amplitude waveform for table 19
Figure 15. Power supply transient amplitude test circuit for table 19
Standardization Document Improvement Proposal
Instructions

Modules, Standard Electronic High Performance Address Generation Module, Key Code CWK

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