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Page Title:
Figure 9. Test circuit for static tests notes |
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|  MIL-M-38510/118B
NOTES:
1. Heavy current paths (I ≥ 1.0 A) are indicated by bold lines.
2. Kelvin connections must be used for all output current and voltage measurements.
For device types 03 and 04, output voltage measurements shall be made 1/8 inch below the case.
3. The output offset voltage shall be adjusted to zero with the device under test (DUT) removed.
The operational amplifier stabilization networks may vary with test adapter construction.
Alternate drive circuits for the 2N6296 may be used to develop the proper load current and input
voltage pulses. These circuits shall require the approval of the qualifying activity.
4. Relay switch positions are defined in table III.
5. Load currents of 5 mA may be established via the load resistors R1 and R2. All other load currents
shall be established via the pulse load circuit. Resistors R1 and R2 shall have a tolerance ≤ 0.1 %
for device types 01 and 02.
6.
The pulse generator for the pulse load circuit shall have the following characteristics:
a. Pulse amplitude = -10 ( |IL| - VO / ( R1 + R2 )) volts.
b. Pulse width = 1.0 ms (unless otherwise stated).
c. Duty cycle = 2% (maximum).
Load currents shall be determined by the voltage measured across the 1 Ω resistor.
7.
Measurements shall be made 0.5 ms after the start of the pulse.
|VIN| (LOW) and |VIN| (HIGH) per table III herein.
8.
VRLINE = VB VA.
9.
The output voltage is sampled at specified intervals. Strobe pulse width is 100 s maximum.
10.
IL (minimum) and IL (maximum) per table III herein.
11.
12. VRLOAD = VD VC.
13. VRTH = VD VE.
14. IOS = (IL) amps.
FIGURE 9. Test circuit for static tests Continued.
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