Microcircuits, Digital, NMOS, 65,536 BIT, Random Access Memory (RAM), Monolithic Silicon

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Microcircuits, Digital, NMOS, 65,536 BIT, Random Access Memory (RAM), Monolithic Silicon

Microcircuits, Digital, NMOS, 65,536 BIT, Random Access Memory (RAM), Monolithic Silicon
Alphanumeric particle induced error rate
Table 1. Electrical performance characteristics
Table 1. Electrical performance characteristics-cont.
Table 1. Electrical performance characteristics-cont.
Lead material and finish
Microcircuit group assignmet
Group C inspection
Figure 1. Terminal connections
Figure 2. Block diagram
Figure 3. Truth table
Figure 4. Burn-in and steady state life test circuit
Figure 5. Switching time test circuit
Figure 6. Read cycle waveforms
Figure 7. Write cycle waveforms
Figure 8. Read/write, read/modify/write cycle waveforms
Figure 9. "RAS-ONLY" refresh cycle waveforms
Figure 10. Timing waveforms for active current (ICCI) measurements
Figure 11. Timing waveforms for refresh current (Icc3) measurements
Table 3. Group A inspection for device types 01 and 02
Table 3. Group A inspection for device types 01 and 02-cont.
Table 3. Group A inspection for device types 03
Table 3. Group A inspection for device types 03-cont.
Table 4A. Recommended timing set designation for screening table I limits (device type 01 and 02)
Table 4A. Recommended timing set designation for screening table I limits (device type 01 and 02)-cont.
Table 4A. Recommended timing set designation for screening table I limits (device type 03)
Table 4B. Recommended timing set designation for screening table 1 limits (device type 03)-cont.
High voltage (Vzap) test of input protection circuits
Application and operation guidelines
Refresh operations
Appendix. Functional Algorithms and Timing sets
Marching Columns, Initial Data Background = All "0"
Refresh test (Cell Retention)
RAS-Only/Refresh Test
Instructions
Standardization Document Improvement Proposal
Custodian

Microcircuits, Digital, NMOS, 65,536 BIT, Random Access Memory (RAM), Monolithic Silicon

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