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Page Title:
Figure 7. Synchronous switching test circuit for device type 02 and 03. |
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|  MIL-M-38510/2G
NOTES:
1. Clock input characteristics for tPLH, tPHL (clock to output), Vgen = 3 V, t1 = t0 ≤ 10 ns, tp (clock)
= 25 ns, and PRR = 1 MHz. All J and K inputs are at 2.4 V. When testing fMAX the clock
input characteristics are Vgen = 3 V, t1 = t0 ≤ 10 ns, tp (clock) = 20 ns, and PRR = 10 MHz for
subgroups 9, 10, and 11.
2. All diodes are 1N3064, or equivalent.
3. CL = 50 pF minimum (including jig and probe capacitance).
4. RL = 390Ω 5%
FIGURE 7. Synchronous switching test circuit for device type 02 and 03.
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