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Page Title:
Table 3. Group A inspection for device type 02-cont. |
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|  FOOTNOTES:
A. Apply input pulse:
2.5 V minimum/5.5 V maximum
0V
B. Apply input pulse:
2.5 V minimum/5.5 V maximum.
0V
C. VIN = 2.5 V.
D. VIN = 0.4 V.
E. Test numbers 54 through 99 shall be run in sequence.
F. Output voltages shall be either: (1) H ≥2.5 V minimum and L ≤0.4 V maximum when using a high speed checker double comparator; (2) H ≥1.5 V and L <1.5 V when using a high
speed checker single comparator.
G. fMAX minimum limit specified is the frequency of the clock input pulse. The output frequency shall be one-half of the input clock frequency. The input frequency on the parallel input
shall be one-half of the clock input frequency and the parallel input shall be shifted such that the parallel input ↑ and ↓ are coincident with the clock ↓ . Rise and fall times ≤ 6 ns.
Input peak voltage 3 to 5 volts.
J. 3.0 V minimum/5.0 V maximum.
1/ This pulse must occur after the clear pulse.
2/ IIL limits (mA) min/max values for circuits shown:
Parameter
Terminal
A
B
C
D
E
F
G
IIL1
CLR
-.16/-.4
-.11/-.35
-.16/-.4
-.12/-.35
-.12/-.36
-.12/-.36
-.16/-.4
J, K, AIN,
"
-.16/-.4
"
-.16/-.4
-.105/-.345
"
"
BIN, CIN, DIN
Shift load
"
-.08/-.3
"
-.12/-.36
-.12/-.36
"
"
CLK
"
-.03/-.3
-.20/-.44
-.12/-.36
-.12/-.36
"
-.15/-.38
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