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Page Title:
Table 3. Group A inspection for device type 05-cont. |
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|  FOOTNOTES:
A.
Apply input pulse:
2.5 V minimum/5.5 V maximum.
0V
B.
VIN = 2.5 V.
C.
VIN = 0.4 V.
D.
Test numbers 42 through 81 shall be run in sequence.
Output voltages shall be either: (1) H ≥2.5 V minimum and L ≤0.4 V maximum when using a high speed checker double comparator; (2) H ≥1.5 V and L ≤1.5 V when using a high speed checker single
E.
comparator.
F.
fMAX minimum limit specified is the frequency of the clock input pulse. The output frequency shall be one-half of the input clock frequency. The input frequency on the AIN data shall be one-half of the clock
input frequency and the AIN shall be shifted such that the AIN and are coincident with the clock. Rise and fall times ≤ 6 ns. Input peak voltage 3 to 5 volts.
G.
3.0 V minimum/5.0 V maximum.
J.
Apply input pulse:
2.5 V minimum/5.5 V maximum
0V
1/
One pulse minimum.
2/
Two pulses minimum.
3/
Three pulses minimum.
4/
Four pulses minimum.
5/
Five pulses minimum.
6/
Six pulses minimum.
7/
Seven pulses minimum.
8/
Eight pulses minimum.
9/
At the manufacturer's option, IOS tests 33 through 40, the following alternate procedure may be used; apply 2.75 volts @; test 33, QA , test 34, QB, test 35, QC, test 36, QD, test 37, QE, test 38, QF, test 39,
QG, test 40, QH, and min/max limits of -7.5/-50 mA.
10/
IIL limits (mA) min/max values for circuits shown:
Parameter
Terminal
A
B
C
D
E
F
G
IIL1
AIN, BIN
0/-.34
-.10/-.34
-.16/-.40
-.16/-.40
-.135/-.370
-.12/-.36
-.16/-.40
"
"
CLK
0/-.4
-.16/-.4
-.12/-.36
-.20/-.44
"
"
"
CLR
0/-.4
-.16/-.4
-.12/-.36
-.16/-.40
"
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