Microcircuits, Digital, N-Channel, Silicon Gate Monolithic 16-BIT Microprocessor

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Microcircuits, Digital, N-Channel, Silicon Gate Monolithic 16-BIT Microprocessor

Microcircuits, Digital, N-Channel, Silicon Gate Monolithic 16-BIT Microprocessor
Terminal connections and pin assignments
Table 1. Electrical performance characteristics
Table 1. Electrical performance characteristics-cont.
Table 1. Electrical performance characteristics-cont.
Table 1. Electrical performance characteristics-cont.
Table 1. Electrical performance characteristics-cont.
Microprocessor instructions
Qualification extension
Figure 1. Case outline X (48-lead, 9/16" x 2-7/16" dual-in-line package)
Figure 1. Case outline X (48-lead, 9/16" x 2-7/16" dual-in-line package)-cont.
Figure 2. Terminal connections and pin assignments
Figure 2. Terminal connections and pin assignments (Device types 02 and 04)
Figure 2. Terminal connections (case outline Z, 52-terminal SQ chip carrier)
Figure 2. Terminal connections (case outline Y, 44- terminal SQ chip carrier)
Figure 3. Functional block diagram
Figure 4. Dynamic burn-in and life test
Figure 4. Dynamic burn-in and life test (Device types 02 and 04)
Figure 5. Output load circuit for functional and ac testing
Table 3. Group A Inspection for device types 01 and 03
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Group A Inspection for device types 01 and 03-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 3. Table 3. Group A Inspection for device types 02 and 04-cont.
Table 4. Input conditions for device types 01 and 02 functional tests
Table 4. Input conditions for device types 01 and 02 functional tests-cont.
Table 4. Input conditions for device types 01 and 02 functional tests-cont.
Table 4. Input conditions for device types 01 and 02 functional tests-cont.
Table 4. Input conditions for device types 01 and 02 functional tests-cont.
Table 4. Input conditions for device types 03 and 04 functional tests
Table 4. Input conditions for device types 03 and 04 functional tests-cont.
Table 4. Input conditions for device types 03 and 04 functional tests-cont.
Table 4. Input conditions for device types 03 and 04 functional tests-cont.
Table 4. Input conditions for device types 03 and 04 functional tests-cont.
Figure 6. AC timing diagram (memory read/write timing)
Figure 6. AC timing diagram (input/output timing)
Figure 6. AC timing diagram (interrupt and segment trap acknowledge cycle)
Figure 6. AC timing diagram (bus request acknowledge cycle)
Figure 6. AC timing diagram (miscellaneous signals)
Table 5. Test Vectors
Table 6. Microprocessor instructions for all device types
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Table 6. Microprocessor instructions for all device types-cont.
Figure 7. High voltage (Vzap) test circuit
Test vector table
Terms and definitions-cont.
Substitutability

Microcircuits, Digital, N-Channel, Silicon Gate Monolithic 16-BIT Microprocessor

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