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Page Title:
Figure 2. Truth tables and timing diagrams. |
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|  MIL-M-38510/9E
Device type 01
INPUTS
OUTPUTS
QB
QC
QD
QA
MODE
CLOCKS
SERIAL
PARALLEL
CONTROL 2 (L)
1(R)
A
B
C
D
H
H
X
X
X
X
X
X
QA0
QB0
QC0
QD0
X
X
a
b
c
d
a
b
c
d
H
↓
d
d
X
X
H
†
QC†
QD†
↓
QBn
QCn
QDn
QB
L
L
H
X
X
X
X
X
QA0
QB0
QC0
QD0
L
X
H
X
X
X
X
H
↓
QBn
QCn
QAn
L
X
L
X
X
X
X
L
↓
QBn
QCn
QAn
L
L
X
X
X
X
X
↑
QB0
QC0
QD0
QA0
L
L
X
X
X
X
X
↓
QB0
QC0
QD0
QA0
L
H
X
X
X
X
X
↓
QB0
QC0
QD0
QA0
H
L
X
X
X
X
X
↑
QB0
QC0
QD0
QA0
H
H
X
X
X
X
X
↑
QB0
QC0
QD0
QA0
†
= Shifting left requires external connection of QB to A, QC to B, and QD to C. Serial data is entered at input D.
H = high level (steady state), L = low level (steady state), X = irrelevant (any input including transitions)
↓ = transition from high to low level, ↑ = transition from low to high level
a, b, c, d = the level of steady state input at inputs A, B, C, or D, respectively.
QA0, QB0, QC0, QD0 = the level of QA, QB, QC or QD respectively, before the indicated steady state input
conditions were established.
QAn, QBn, QCn, QDn = the level of QA, QB, QC or QD respectively, before the most recent ↓ transition of the
clock.
Device type 02
INPUTS
OUTPUTS
CLEAR
PRESET
PRESET
CLOCK
SERIAL
QB
QC
QD
QE
QA
ENABLE
A
B
C
D
E
L
L
X
X
X
X
X
X
X
L
L
L
L
L
L
X
L
L
L
L
L
X
X
L
L
L
L
L
H
H
H
H
H
H
H
X
X
H
H
H
H
H
H
H
L
L
L
L
L
L
X
QB0
QC0
QD0
QE0
QA0
H
H
H
H
H
L
H
L
H
L
X
H
QD0
QB0
H
L
X
X
X
X
X
L
X
QB0
QC0
QD0
QE0
QA0
H
H
H
L
X
X
X
X
X
↑
QBn
QCn
QDn
QAn
L
L
H
L
X
X
X
X
X
↑
QAn QBn QCn
QDn
H = high level (steady state), L = low level (steady state),
X = irrelevant (any input including transitions), ↑ = transition from low to high level
QA0, QB0, etc. = the level of QA, QB, etc. respectively, before the indicated steady state input
conditions were established.
QAn, QBn, etc. = the level of QA, QB, etc. respectively, before the most recent ↑ transition of the
clock.
Figure 2. Truth tables and timing diagrams.
13
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