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Page Title:
Figure 2. Truth tables and timing diagrams device type 03 |
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|  MIL-M-38510/9E
Device type 03
INPUTS
OUTPUTS
CLEAR
CLOCK
A
B
QB...
.QH
QA
L
X
X
X
L
L
L
H
L
X
X
QB0
QH0
QA0
H
H
H
H
↑
QGn
QAn
H
L
X
L
↑
QGn
QAn
H
X
L
L
↑
QGn
QAn
H = high level (steady state), L = low level (steady state),
X = irrelevant (any input including transitions),
↑ = transition from low to high level
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before
the indicated steady state input conditions were established.
QAn, QGn = the level of QA or QG before the most recent ↑ transition
of the clock; indicates a one bit shift.
Device type 04
INPUTS
INTERNAL
SHIFT/
CLOCK
CLOCK
SERIAL
PARALLEL
OUTPUTS
OUTPUT
LOAD
INHIBIT
A....H
QA
QB
QH
L
X
X
X
a....h
a
b
h
H
L
L
X
X
QB0
QH0
QA0
H
X
H
H
L
↑
QGn
QAn
L
X
L
H
L
↑
QGn
QAn
X
X
QA0
H
H
↑
QH0
QB0
H = high level (steady state), L = low level (steady state),
X = irrelevant (any input including transitions),
↑ = transition from low to high level
a . . . . h = the level of steady state input at inputs A thru H, respectively.
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before
the indicated steady state input conditions were established.
QAn, QGn = the level of QA or QG before the most recent ↑ transition
of the clock.
Figure 2. Truth tables and timing diagrams Continued.
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