Multiplexer, TD-1236/G

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Multiplexer, TD-1236/G

Multiplexer, TD-1236/G
Specifications, standards, and handbooks
Other Government documents, drawings, and publications
Order of precedence
Semiconductor devices and integrated circuits
Balanced equipment-side signal characteristics
Resync command, waveform parameters
Table 1. TD-1236/G group rates
Table 2. TD-1236/G group rates
Table 2. TD-1236/G group rates-cont.
Frame acquisition
Group input buffering
Built-in test equipment (BITE) and alarms
Timing modes
Service conditions
Electromagnetic interference (EMI)
Unit subassembly electrical performance
Systems safety engineering
Responsibility for compliance
First article units
Table 4. First article inspections
Table 4. First article inspections-cont.
Quality conformance inspection of equipment before preparation for delivery
Order of inspection within Group A
Table 5. Group A inspection
Sampling for Group C inspections
Order of inspection within group C
Table 7. Group C inspection
Reinspection of conforming group C sample units
Electrical preconditioning (burn-in)
Table 9. Standard test equipment
Table 10. Special test equipment
Table 11. Government furnished equipment (GFE)
Table 12. TD-1236/G interface connections
Balanced equipment-side signal characteristics
Signal balance
Receiver dynamic range
Input load impedance
External clock/data phasing
Resync command voltage
Multiplexing
Table 13. Control Settings on UUT for Single Group Input Tests
Rate Combination tests
Frame Acquisition time
Detection of out-of-sync
Idle filler pattern
Prime power
Built-in test equipment (BITE) and alarms
Group data error check
Environmental full duplex signal detection test
Service conditions tests
Low pressure (altitude)
Vibration and shock
Reliability test conditions
System safety design verification check list
Quality conformance inspection of packaging
Table 14. Packing inspection provisions
Packing and marking
Intended use
Location of operational inspection
Government-furnished property
Figure 1. Burn-in
Figure 2. Alternate timing source
Figure 3. Line-to-line voltage levels
Figure 4. Clock/data phasing
Figure 5. Delay measurement (clock/data phasing)
Figure 6. Offset voltage
Figure 7. Rise and fall slopes (slew rate)
Figure 8. Receiver sensitivity
Figure 9. Input load impedance
Figure 10. Clock Asymmetry
Figure 11. External clock/data phasing
Figure 12. Resync command voltage; waveform
Figure 13. Group resync command voltage: waveform
Figure 14. Frame squelch
Figure 15. Multiplexing: single group input
Figure 16. Multiplexing: rate combination
Figure 17. Faming test
Figure 18. False frame lock
Figure 19. Idler filler patter
Figure 20. Buffer overflow
Figure 21. Power variation
Figure 22. Unit Performance electrical tests
Instructions
Standardization Document Improvement Proposal

Multiplexer, TD-1236/G

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