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Page Title:
Central Data Processor Interface |
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| MIL-N-81497A(AS)
3.4.3.4.4 (Continued)
A fixed count of 22 shift clock pulses shall
(1)
be generated by an external computer at a
rate of 250 KHz.
Sampling of a particular data word shall take
(2)
100 SEC or less and shall not occur more
often than once every 30 milliseconds (MS)
in response to the external computer select
signals, however, all three words can be
called immediately after each other or
dispersed throughout the 30 MS period.
All data shall be transmitted on one data
(3)
line (twisted pair).
Three select gates shall be provided (one
(4)
for each computer signal). The three select
gates shall be initiated non-simultaneously.
Each select gate will stay in the logic 1
state until the 22 bits have been clocked
out. Upon completion of receipt of the output
signal the select gate signal shall be removed.
The form of the transmitted words shall be:
(5)
the first 4 bits are logic O, the next 3
bits are identifier bits (001 for VN, 010
for VE and 100 for true heading) and the last
15 of the 22 pulses are data bits.
Data and control signals shall be logic 1:
(6)
0 0.5V, and logic 0: +4 1V
Clock pulses of square wave shape and +4V
(7)
amplitude shall be supplied by the external
data processor within a time period of 2 to
8 SEC after the transmission of the enter
signal by the equipment [3.4.3.4.4.(10)1.
Leading edge is defined as negative going
(8)
slope from +4 to O V.
Each new data bit shall be available on the
(9)
data shift line within 1 SEC after the
leading edge of the clock pulse.
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