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Central Data Processor Interface -Cont. |
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|  MIL-N-81497A(AS)
3.4.3.4.4 (Continued)
(10) The enter signal from the equipment to the
external computer must acknowledge acceptance
of the select signal (go from logic 0 to
logic 1) within 7 SEC after the leading
edge of the select signal.
(11) Enter signal must return to logic 0 (+4V)
within 3 SEC after lagging edge of select
signal.
(12) All control lines shall be a two pin connection
to a pair of twisted wires.
(13) All interface characteristics shall be as
shown in Figure 4.
(14) The output serial data format shall be:
Velocity (VNS and VEW)
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