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|  MIL-N-85005A(AS)
Form Factor - The Digital Display Indicator, exclusive of
3.5.3.2
front panel protrusions, attachment points, and connector projections,
shall be formed within the following maximum dimensions (inches).
Width
Height
Depth
5.75 (behind mounting surface)
5.750
3.000
Weight - The weight of the Digital Display Indicator
3.5.3.3
shall not exceed 3.0 pounds.
Contents - The Digital Display Indicator shall contain
3.5.3.4
logic circuitry functions interfacing the Keyer Control.
3.5.3.4.1 Data Serial Train - The data serial train for all four
sections of the Digital Display Indicator shall be entered on a common
line. Selection shall be by presenting a gated clock on only one of the
four clock inputs. Data for alphas shall be coded American Standard
Code for Information Interchange (ASCII), and the code for numerics
shall be 4-bit binary-coded decimal (BCD). Individual bits shall
control decimals, degrees, and non-BIT status lights.
3.5.3.4.2 Logic Signal Circuitry - Logic signal circuitry shall be
of the differential line receiver type, similar to A9615, and shall be
compatible with signals supplied by a differential line driver similar
to A9614. Logic level definition shall be as presented in Figure 4.
3.5.3.4.3 Gated Clock Inputs - Four dedicated clock inputs (one for
each display section) shall be provided. The positive - going clock, on
positive line, shall appear on one input at one time during updating of
the section. Clock gating shall be in word lengths of 16 clock-cycles
with word numbers as listed:
Section I - 3 words
Section II, III, and IV - 2 words
Waveforrn and synchronization with data input shall be as depicted
in Figure 9.
3.5.3.4.4 Reset Input - The reset input shall be a differential
logical "1" going pulse of 2 sec duration preceding any display update.
The reset pulse shall be sent out by the Keyer Control whenever a
command word is received from the NC. Based on this logic, a reset
pulse can be received without a subsequent series of gated-clock signals,
however a gated-clock signal shall always be preceded by a reset pulse
(Figure 9).
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