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|  MIL-N-85005A(AS)
3.5.3.4.7.1 Display Test Signal Output - A steady state logic
level shall be a simultaneous output to the Keyer Control with the lamp
test of the display as listed:
Logical "1" = Lamps extinguished
Logical "0" = Lamps illuminated
BIT Signal Output - A steady state logic level shall
3.5.3.4.7.2
be output to indicate actuation of the BIT pushbutton switch as listed:
Logical "1" = Switch depressed
Logical "0" = Switch released
Displays and Controls - The Digital Display Indicator
3.5.3.5
shall contain designated controls and displays with positional placements
and labeling depicted in Figure 10. Labeling shall be transilluminated
for low-ambient viewing. Display illumination shall be controlled by
the rotatable DIM knob. The knob shall be finished compatible gray per
FED-STD-595. All lighting elements shall be front replaceable. Panel
illumination shall be white per MIL-P-7788 derived from 5 VAC excitation
controlled by a dimmable 26 VAC cockpit dim control. The three Advisory
and two BIT Status Indicators shall be identified by illumination of an
amber light mounted immediately below each listed indicator.
3.5.3.5.1 Data Display - The data display shall consist of three
rows of alphanumeric characters. The top row shall contain six alpha-
numeric characters, primarily of interactive routine. The middle and
bottom rows shall each contain one alpha and eight numeric characters.
The two rows of data shall allow simultaneous display of logically
grouped parametric pairs. Data insertion shall first be presented at
extreme left as a parameter identifier with inserted numeric values
first appearing at extreme right, shifting left across display in
sequence of entry. The displays shall be segmented incadescent type,
with an external red filter.
Test Control - Test shall be effected by actuating
3.5.3.5.2
the two PBI's indicated.
LMP - All filaments of the Data Display Indicator
lamps and the five Advisory Status Indicator
lamps shall illuminate simultaneously with
steady state logic level signal output per
Paragraph 3.5.3.4.7.1.
BIT - Steady state logic level shall be output per
Paragraph 3.5.3.4.7.2 and 3.5.2.4.4.7.
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