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|  MIL-T-63534(AR)
3.6.1 .2.5 Normal stow mode. With all mode switching voltages at zero Vdc
(Pin J2-U and Pin J1-K), the azimuth demodulator output voltage at Pin J2-D
shall be as specified in 3.6.1 .2.3 with regard to the azimuth-stow adjustment.
The elevation demodulator output voltage at Pin J2-P shall be zero Vdc when
the input voltage at Pin J3-D is 1.92 Vrms (15 percent) and 180 degrees out
of phase with the voltage on Pin J2-L.
3.6.1.2.6 Output drive and control.
3.6.1 .2.6.1 Azimuth output drive and control. With 26.5 (5) Vdc applied
to Pins J1-K, and left, or right limit voltages applied at J3-A and J3-B, the
magnitude of the 400 Hz sight azimuth error signal on Pin J1-M shall control
the pulse width on the turret left drive Pin J4-D or the turret right drive
respectively Pin J4-F. See paragraph 3.6.1.2.14 for current limits. The
phase of the signal shall determine whether the left drive output (Pin J4-D)
or the right drive output (Pin J4-F) iS enabled. A signal on pin J1-M in
phase with the reference voltage on Pin J2-L shall enable the right drive
output for a pulse width modulated 28 Vdc (high level) on Pin J4-F and shall
disable the left drive output on Pin J4-D. An out of phase signal on Pin J1-M
shall enable the left drive output for a pulse width modulated 28 Vdc (high
level) on pin J4-D and shall disable the right drive output on Pin J4-F. The
pulses of 28 Vdc (high level) peak amplitude Of varying width at pin J4-D or
Pin J4-F shall be at a repetitive rate of 600 Hz and shall supply a minimum
output load (split series d-c motor) of 0.1 ohm in series with 150
microhenries, +20 percent, Which saturates at 30 amperes. Each output shall
have a coasting diode for protection against back electromotive force. The
load return shall be on Pin J4-E. The following threshold levels apply:
A voltage on Pin J3-A (azimuth limit-left) of less than 5 Vdc
shall disable the left drive output on Pin J4-D. Voltages between 20 and 30
Vdc on Pin J3-A shall enable the output at Pin J4-D.
b. A voltage on Pin J3-B (azimuth limit-right) of less than 5 Vdc
shall disable the right drive output on Pin J4-F. Voltages between 20 and 30
Vdc on Pin J3-B shall enable the output on Pin J4-F.
3.6.1 .2.6.2 Elevation output drive and control. With 26.5 (+5) Vdc
applied to Pins J1-K, J3-C and J3-K, the magnitude of the 400 Hz signal on Pin
J1-B shall determine whether the down drive output (pin J4-A) or the UP drive
output (Pin J4-C is enabled. A signal on Pin J1-B in phase with the
reference voltage on Pin J2-L shall enable the up drive output for a pulse
width modulated 28 Vdc (high level) on Pin J4-C and shall disable the down
drive output on Pin J4-A. An out of phase signal on Pin J1-B shall enable
down drive output for a pulse width modulated 28 VdC (high level) On pin J4-A
and shall disable the up drive output on Pin J4-C. The pulses of 28 Vdc (high
level) at Pin J4-A or Pin J4-C shall be at a repetitive rate of 600 Hz and
shall supply a minimum output load of 0.1 ohm in series with 150 microhenries,
+20 percent which saturates at 30 amperes. Each output shall have a coasting
diode for protection against back electromotive force. The load return shall
be on Pin J4-B. The following threshold levels apply:
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