output at Pin J2-X shall remain at 28 (2) Vdc for 350 (100) ms before
returning to 0 (0.5) Vdc. When the interlocked trigger signal is applied
first, and then, the fire volts pulse train is applied, the output at Pin J2-X
shall rise to 28 (2) Vdc following a maximum delay of 6 ms after the beginntng
of the second fire volts input pulse. When the fire volts input pulses are
removed, the output shall remain for 350 (100) ms after start of the last
126.96.36.199.3 SCAS circuitry with low frequency pulse input. The output at
Pin J2-X shall change from 28 (2) Vdc to 0(0.5) Vdc if the period between
the fire volts pulse input increases beyond 165 milliseconds.
188.8.131.52 Depression limit component assembly. With input power as
specified i n3.1.3 and with the additional inputs described below, the
following outputs shall occur.
184.108.40.206.1 Depression limit circuit, no-limit mode. When the following
inputs are applied, outputs shall occur as specified below:
Voltage at Pin J1-D shall be
0.5 V rms, 400 Hz, in phase
equal to the input 7%.
with 26 Vac at Pin J2-U
With return to Pin J1-V
Voltage at Pin J1-D shall
0.5 V rms, 400 Hz, 1800 out
be equal to the input 7%.
of phase with 26 Vac input
at Pin J2-U
With return to Pin J1-W
When either of the above two inputs are applied and 1.5 V rms is applied at
Pin J1-j, either in-phase or 180 degrees out of phase, with a 26 Vac input at
Pin J2-U and the return to Pin J2-g, there shall be no effect on the output at
3.6.1 .4.2 Depression limit circuit, limit mode. When 28 (+0.5 -O) Vdc is
applied to PinJ2-j with return to Pin J2-g, the following outputs shall occur
when the specified inputs are applied.